• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.1
• /
• pp.173-180
• /
• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.4
• /
• pp.671-678
• /
• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.16 no.5
• /
• pp.233-240
• /
• 2021

We propose a novel, highly accurate approximate multiplier using different types of inexact 4-2 compressors. The importance of low hardware costs leads us to develop approximate multiplication for error-resilient applications. Several rules are developed when selecting a topology for designing the proposed multiplier. Our highly accurate multiplier design considers the different error characteristics of adopted compressors, which achieves a good error distribution, including a low relative error of 0.02% in the 8-bit multiplication. Our analysis shows that the proposed multiplier significantly reduces power consumption and area by 45% and 26%, compared with the exact multiplier. Notably, a trade-off relationship between error characteristics and hardware costs can be achieved when considering those of existing highly accurate approximate multipliers. In the image blending, edge detection and image sharpening applications, the proposed 8-bit approximate multiplier shows better performance in terms of image quality metrics compared with other highly accurate approximate multipliers.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.3
• /
• pp.594-599
• /
• 2007

A dosed-loop sensorless stroke control system for a linear compressor has been designed. The motor parameters are identified as a function of the piston position and the motor current. They are stored in ROM table and used later for the accurate estimation of piston position. Also it was attempted to approximate the identified motor parameters to the 2nd-order surface functions. The 2nd-order surface functions are divided into 2 or 4 sub-sections for more precise identification of motor parameters. Some experimental results are given in order to show the feasibility of the proposed control schemes for linear compressors.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.19 no.11
• /
• pp.1151-1157
• /
• 2009

Ensuring both product quality and reducing material cost are important issue for the design of the piping system of an air conditioner outdoor unit. This paper describes a shape optimization that achieves mass reduction of an air conditioner piping system while satisfying two design constraints on resonance avoidance and the maximum stress in the pipes. In order to obtain optimized design results with various analysis fields considered simultaneously, an automated multidisciplinary analysis system was constructed using PIAnO v.2.4, a commercial process integration and design optimization(PIDO) tool. As the first step of the automated analysis system, a finite element model is automatically generated corresponding to the specified shape of the pipes using a morphing technique included in HyperMesh. Then, the performance indices representing various design requirements (e.g. natural frequency, maximum stress and pipe mass) are obtained from the finite element analyses using appropriate computer-aided engineering(CAE) tools. A sequential approximate optimization(SAO) method was employed to effectively obtain the optimum design. As a result, the pipe mass was reduced by 18 % compared with that of an initial design while all the constraints were satisfied.