• ETRI Journal
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• v.25 no.6
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• pp.510-516
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• 2003

In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 ${\mu}m$ technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.26-33
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• 2010

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.

• Korean Journal of Mathematics
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• v.7 no.1
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• pp.85-101
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• 1999

Let $p$ be analytic in the unit disc U and let $q$ be univalent in U. In addition, let ${\Omega}$ be a set in C and let ${\psi}:c^3{\times}U{\rightarrow}C$. The author determines conditions on ${\psi}$ so that $$\{{\psi}(p(z),zp^{\prime}(z),z^2p^{{\prime}{\prime}}(z);z){\mid}z{\in}U\}{\subset}{\Omega}{\Rightarrow}p(U){\subset}q(U)$$. Applications of this result to differential inequalities, differential subordinations and integral inequalities are presented.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.2
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• pp.85-92
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• 2022

Currently, various researches on electric vehicle battery systems have been conducted from the viewpoint of safety and performance for SoC, SoH, etc. However, it is difficult to build a precise electrical model of a battery system based on the chemical reaction and SoC prediction. Experimental measurements and predictions of the battery SoC were usually performed using dynamometers. In this paper, we construct a simulation model of an electric vehicle system using Matlab Simulink, and confirm the response characteristics based on the vehicle test driving profiles. In addition, we show that it is possible to derive the correlation between the SoC, voltage, and current of the battery according to the driving time of the electric vehicle in conjunction with the BMS model.

• ETRI Journal
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• v.44 no.5
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• pp.849-858
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• 2022

Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layerwise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.363-372
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• 2015

Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.365-369
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• 2002

In this paper, DC motor controller has been designed by using SoC. SoC is short for System on a chip. This is a methodology that both a processor and some applications are integrated in a chip. In order to design this system based on SoC, PIC 16C57 has been selected as a processor because it has not too many instruction sets and simple data path named a harvard structure. And motor control module has been programmed by using VHDL. The advantages of the design based on SoC are as follows: simple structure, high speed working, easily verifying and simulating the system.

• ETRI Journal
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• v.42 no.4
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• pp.491-504
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• 2020

We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on-chip memory. Complementing the hardware is an intuitive and user-friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40-TFLOP STC that includes 32k arithmetic units and over 36 MB of on-chip SRAM, our baseline implementation of AB9 consists of a 1-GHz quad-core setup with other various industry-standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general-purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28-nm process with a chip size of 17 × 23 ㎟. Delivery is expected later this year.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.1
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• pp.45-55
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• 2019

DEX file and share objects (also known as the SO file) are important components that define the behaviors of an Android application. DEX file is implemented in Java code, whereas SO file under ELF file format is implemented in native code(C/C++). The two layers - Java and native can communicate with each other at runtime. Malicious applications have become more and more prevalent in mobile world, they are equipped with different evasion techniques to avoid being detected by anti-malware product. To avoid static analysis, some applications may perform malicious behavior in native code that is difficult to analyze. Existing researches fail to extract the call relationship which includes both Java code and native code, or can not analyze multi-DEX application. In this study, we design and implement a system that effectively extracts the call relationship between Java code and native code by analyzing DEX file and SO file of Android application.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.8
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• pp.4227-4240
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• 2019

In this paper, we present our proposed magnetic induction based wireless communication system. The proposed system is designed to perform communication as well as distance measurement in underground environments. In order to improve the communication quality, we propose and implement the adaptive channel compensation technique. Based on the fact that the channel may be fast time-varying, we keep track of the channel status each time the data is received and accordingly compensate the channel coefficient for any change in the channel status. By using the proposed compensation technique, the developed platform can reliably communicate over distances of 10m while the packet error rate is being maintained under 5%. We also implement the distance measurement block that is useful for various applications that should promptly estimate the location of nearby nodes in communication. The distance between two nodes in communication is estimated by generating a table describing pairs of the magnetic signal strength and the corresponding distance. The experiment result shows that the platform can estimate the distance of a node located within 10m range with the measurement error less than 50cm.