• Journal of Broadcast Engineering
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• v.21 no.6
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• pp.944-956
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• 2016

In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.236-250
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• 2016

Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1071-1073
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• 2000

The use of HDL(Hardware Description Language) is now central to the ASIC(Application Specific Integrated Circuit). HDL-based ASIC can simplify the process of development and has a competition in market because it reduce the consuming time for the design of IC(Integrated circuit) in system level. Therefore, the development of power electronics system on chip (SOC), to design microcontroller and switching logic as one chip, is required extremely for the purpose of having reliability and low cost in power electronics which is based on switching elements. The major application of SOC is variable converter, active filter inverter for induction motor. UPS and power supply with a view to reducing electro-magnetic pollution.

• The Magazine of the IEIE
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• v.31 no.8
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• pp.44-51
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• 2004

최근 SoC (System on Chip) 기술의 발전으로 최대 10 Gbps의 처리율을 갖는 네트워크 프로세서가 개발되고 있다. 네트워크 프로세서는 기존의 ASIC (Application Specific Integrated circuit)또는 FPGA (Field Programmable Gate Array) 등 하드웨어가 수행하던 고속의 패킷 처리 기능을 소프트웨어 기반으로 처리하도록 함으로써 다양한 기능의 패킷 처리를 저비용으로 단시간 내에 개발 할 수 있는 장점을 갖고 있다.(중략)

• ETRI Journal
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• v.39 no.4
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• Tribology and Lubricants
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• v.29 no.3
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• pp.143-148
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• 2013

In this study, several sensor parts used to obtain better signal stability are designed, a separate control circuit for the sensor is developed, and the results obtained using this control circuit are analyzed. The capacitances of the whole sensor system are measured using the control circuit connected to an improved flexible printed circuit board and an asymmetric dual sensor coated with a ceramic material. To realize good discrimination for a small change in the measured capacitance as the engine oil deteriorates, a commercial application-specific integrated circuit is installed on the control circuit as a capacitance-to-digital converter. The absolute error of a measured signal is found to be approximately ${\pm}4fF$.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• 한국전자현미경학회:학술대회논문집
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• 2001.11a
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• pp.18-22
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• 2001

A technique to characterize specific site of materials using a combination of a dedicated focused ion beam system(FIB), and Intermediate-voltage scanning transmission electron microscope(STEM) or transmission electron microscope(TEM) equipped with a scanning electron microscope(SEM) unit has been developed. The FIB system is used for preparation of electron transparent thin samples, while STEM or TEM is used for localization of a specific site to be milled in the FIB system. An FIB-STEM(TEM) compatible sample holder has been developed to facilitate thin sample preparation with high positional accuracy Positional accuracy of $0.1{\mu}m$ or better can be achieved by the technique. In addition, an FIB micro-sampling technique has been developed to extract a small sample directly from a bulk sample in a FIB system These newly developed techniques were applied for the analysis of specific failure in Si devices and also for characterization of a specific precipitate In a metal sample.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.695-701
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• 1988

본 연구에서는 구조적 표현의 화상 처리 알고리즘인 BF(Breadth First) 선형 4진 트리 알고리즘(BFQT 알고리즘)의 압축, 재생부를 하드웨어화 하여 ASIC(Application Specific Integrated Circuit)을 설계한다. ASIC과 IBM PC와의 인터페이스를 명시하며, 새로운 하드웨어 알고리즘을 도입하여 ASIC의 세부구조를 설계한다. 소프트웨어로 수행할 때 보다 제안된 ASIC으로 수행할 때가 압축은 약 21배, 재생은 약 4배 빨라지는 것으로 추정된다.