• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.71-77
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• 2015

In this paper, we propose a scheduling method for signal measurement and control algorithm execution in a multi-motor drive controller. The multi-motor controller which is used for vehicle control receives position/velocity command and performs position/velocity control and current control. Internal resource allocation and control algorithm execution timing are very important when one microcontroller is used for multi-motor drives. The control performance of the velocity control system is verified by varying ADC(Analog to Digital Converter) conversion timing and algorithm execution timing using real experiments.

• Journal of Power Electronics
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• v.6 no.2
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• pp.139-145
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• 2006

This paper describes the ultra precise position estimation of a servomotor using a sinusoidal encoder based on Arcsine Interpolation Method for the cost reduction of circuit design. The amplitude and offset errors of the sinusoidal encoder output signals, from the encoder itself and analog signal processing procedures, are effectively compensated and on-line tuned by utilizing a low cost programmable differential amplifier without any special expensive equipment. For a theoretical evaluation of the practical resolution of this system, the relationship between the amplitude of ADC(Analog to Digital Converter) input signal errors and the anticipated resolution is also addressed. The performance of the proposed method is verified by comparing it with speed control characteristics of the servomotor driving system using a digital incremental 50,000ppr encoder in the experiments.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.4
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• pp.573-577
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• 2015

In this paper, we propose a signal processing board suitable for a semi-active laser tracking to detect an optical signal generated from the laser target designator by applying an analog trigger signal, the quadrant photodetector and a high speed ADC(analog-digital converter) sampling technique. We improved the stability by applying the averaging method to minimize the measurement error of a gaussian pulse. To evaluate the performances of the proposed methods, we implemented a prototype board and performed experiments. As a result, we implemented a frequency counter with an error 14.9ns in 50ms. PRF error code has a stability of less than 1.5% compared to the NATO standard. Applying the three point averaging method to ADC sampling, the stability of 28% in X-axis and 22% in Y-axis than one point sampling was improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.583-586
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• 2001

본 논문에서는 다중 대역통과 표본화 이론에 기반하여 1.9GHz IS-95신호와 2.2GHz IMT-2000 신호를 하나의 ADC(analog to digital converter)를 사용하여 동시에 표본화하고 디지털 처리를 수행하는 방법을 제안하고 실험을 통하여 검증하였다. 일반적인 방법으로는 본 논문에서 고려하는 두 신호를 동시에 표본화하기 위해서는 표본화 주파수가 최소한 1GHz 이상의 고속의 ADC를 사용해야 한다. 그러나 현재 ADC의 기술은 광대역의 신호를 직접 더지털화하기에는 아직 미흡하다. 반면에 대역통과 표본화 이론은 기존의 상용 ADC와 기콘의 RF 시스템을 이용하여 다른 대역에 위치한 두 신호를 통합처리 할 수 있는 기반을 제공하고 있다. 본 논문에서는 이러한 대역통과 표본화 이론에 기반을 두고 상용 ADC를 사용하여 표본화 시스템을 구현하여 IS-95신호와 IMT-2000 신호를 표본화하고 이를 컴퓨터에서 디지털 필터를 이용하여 두 신호를 분리하는 실험을 통하여 다중 대역통과 표본화의 적용 가능성을 검증하였다.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.13-18
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• 2024

This paper proposes a circuit utilizing auto zero technology to minimize offset and enhance accuracy in the reference generator and comparator. As evidence, a comparison between pre and post auto zero usage revealed a reduction of approximately 90% in standard deviation. The proposed circuit was implemented using a 55nm CMOS process, with an input frequency of 781.2 Hz. It achieves an Effective Number of Bits (ENOB) of 8.01 bits and a Signal-to-Noise Distortion Ratio (SNDR) of 49.98 dB.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1011-1015
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• 2005

Fully digital controlled 20-bit magnet power supplies have been developed and successfully tested for closed orbit correction of PLS(Pohang Light Source). The new digital power supply has used fiber optics for 25kHz switching of IGBT drivers, and implemented DSP, ADC, Interlock, DCCT cards in a compact 3U-sized 19" chassis. Input/Output low-pass filters suppress harmonics of 60Hz line frequency and switching frequency noise effectively. Overall performance of the power supplies have been demonstrated as +/- 2ppm short-term stability(<1 min), and +/- 10ppm long-term stability(<36 hours). All the existing 12-bit 70 power supplies for vertical correction magnets will be replaced with new digital power supplies during 2005 summer shutdown period. In this paper, we will describe the hardware structure and control method of the digital power supply and the experimental results will be shown.

• Journal of the Semiconductor & Display Technology
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• v.3 no.1
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• pp.1-7
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• 2004

In this paper, we have developed the DC parameters test system which inspects the properties of DC parameters for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC(Analog-to-Digital Converter), DAC(Digital-to-Analog Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. In the comparison of results, the results of the simulation are very similar to the ones of the implementation.

• Proceedings of the KSMRM Conference
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• 2002.11a
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• pp.75-75
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• 2002

목적： 고자장 자기공명영상 시스템 등으로 신호대잡음비가 향상됨에 따라 데이터 측정에서 analog-to-digital converter (ADC)의 quantization noise 가 중요한 시스템 사양으로 부각되고 있다. 특히 자기공명영상은 공간주파수 영역에서 데이터를 측정하기 때문에 dc와 ac간의 신호 차이가 매우 크며, 이러한 dynmic range는 3-D 영상에서 더욱 커진다. 본 연구에서는 다양한 자기총명 영상기법 및 실험 파라미터에 따른 신호의 dynamic range와 ADC의 bit 수에 따른 quantization noise를 살펴봄으로써, 주어진 시스템에 적합한 ADC의 bit 수를 분석하고자 한다. 대상 및 방법： 펄스 시퀀스의 종류, 파라미터, 2D/3D 등에 따른 각 신호의 크기를 수학적으로 모델링하여 신호의 크기를 예측하였다. 또한 whole body MRI 시스템에서 실험을 통하여 신호의 크기를 비교하였다. ADC의 quantization noise를 실험과 시뮬레이션을 통하여 살펴보았다. 시뮬레이션은 test 영상을 Inverse FFT 하여 spatial frequency domain data를 만든 후, 다양한 bit 수의 ADC로 quantization을 한 후 다시 영상을 재구성하였다. 재구성된 영상과 원영상 간의 error가 quantization noise가 된다. 또한 이러한 error가 주파수 영역에서의 error 값과 일치하는지를 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.585-588
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• 2014

This paper presents a self-powered sensor node circuit using photovoltaic and vibration energy harvesting. The harvested energy from a solar cell and a vibration device(PZT) is stored in a storage capacitor. The stored energy is managed by a PMU(Power Management Unit). In order to supply a stable voltage to the sensor node, an LDO(Low Drop Out Regulator) is used. The LDO drives a temperature sensor and a SAR ADC(Successive Approximate Register Analog-to-Digital Converter), and 10-bit digital output data corresponding to current temperature is obtained. The proposed circuit is designed in a 0.35um CMOS process, and the designed chip size including PADs is $1.1mm{\times}0.95mm$.