• Smart Structures and Systems
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• 제19권5호
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• pp.487-497
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• 2017

Semi-active devices use the building's own motion to produce resistive forces and are thus strictly dissipative and require little power. Devices that independently control the binary open/closed valve state can enable novel device hysteresis loops that were not previously possible. However, some device hysteresis loops cannot be obtained without active analog valve control allowing slower, controlled release of stored energy, and is presents an ongoing limitation in obtaining the full range of possibilities offered by these devices. This in silico study develops a proportional-derivative feedback control law using a validated nonlinear device model to track an ideal diamond-shaped force-displacement response profile using active analog valve control. It is validated by comparison to the ideal shape for both sinusoidal and random seismic input motions. Structural application specific spectral analysis compares the performance for the non-linear, actively controlled case to those obtained with an ideal, linear model to validate that the potential performance will be retained when considering realistic nonlinear behaviour and the designed valve control approach. Results show tracking of the device force-displacement loop to within 3-5% of the desired ideal curve. Valve delay, rather than control law design, is the primary limiting factor, and analysis indicates a ratio of valve delay to structural period must be 1/10 or smaller to ensure adequate tracking, relating valve performance to structural period and overall device performance under control. Overall, the results show that active analog feedback control of energy release in these devices can significantly increase the range of resetable, valve-controlled semi-active device performance and hysteresis loops, in turn increasing their performance envelop and application space.

• ETRI Journal
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• 제32권6호
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• pp.911-920
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• 2010

This paper presents a method of designing hybrid analog/asymmetrical square-root (SR) FIR filters. In addition to the conventional frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. This paper also reviews a systematic way to find the discrete-time equivalence of analog parts in a band-limited digital communication system. Thus, a phase equalizer can be easily realized to compensate for the nonlinear phase responses of the analog components. With the hybrid analog/SR FIR filter co-design, examples show that using the proposed method can result in a more robust ISI performance in the presence of the receiver clock jitter.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.238-241
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• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• 로봇학회논문지
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• 제2권3호
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• pp.205-211
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• 2007

In this paper, the prototype of surface EMG (ElectroMyoGram) sensor is developed for the robotic rehabilitation applications, and the developed sensor is composed of the electrodes, analog signal amplifiers, analog filters, ADC (analog to digital converter), and DSP (digital signal processor) for coding the application example. Since the raw EMG signal is very low voltage, it is amplified by about one thousand times. The artifacts of amplified EMG signal are removed by using the band-pass filter. Also, the processed analog EMG signal is converted into the digital form by using ADC embedded in DSP. The developed sensor shows approximately the linear characteristics between the amplitude values of the sensor signals measured from the biceps brachii of human upper arm and the joint angles of human elbow. Finally, to show the performance of the developed EMG sensor, we suggest the application example about the real-time human elbow motion acquisition by using the developed sensor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.909-912
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• 1999

This paper describes realized APC and pre-equalizer circuit, and their operation principle and test results. In analog optical transmitter, constant lasing power control, free of signal clipping and linearity are important considerations. We examined pre-equalizer and APC(Automatic Power Control) circuit to improve the analog optical transmitter performance.

• 융합정보논문지
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• 제9권9호
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• pp.38-43
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• 2019

본 논문에서는 IoT 기기에 내장되는 마이크로컨트롤러의 1개 아날로그 포트를 이용해 1개의 아날로그 입력과 2개의 디지털 스위치 입력을 각각 입력받을 수 있는 방법을 제시하였다. 제시한 방법은 아날로그 입력포트의 입력전압 범위 중 상한선과 하한선을 정해 이 구간은 아날로그 입력 전압을 입력받고, 디지털 스위치들은 각각 상한선과 하한선의 경계를 초과하도록 구성하였다. 제시한 방법의 성능을 입증하기 위해 마이크로컨트롤러를 이용해 회로를 구성하고 실험하였으며, 그 결과 3종류의 입력들이 모두 1개의 아날로그 포트를 이용해 각각 감지할 수 있으므로 본래 필요했던 3개의 입력포트가 1개의 입력포트로, 즉 33%로 줄어드는 효과가 나타남을 확인하였다.

• Current Optics and Photonics
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• 제4권6호
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• pp.483-499
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• 2020

In this paper, a novel analog signature scheme is proposed by modifying an RSA-based digital signature scheme with optical phase-shifting digital holography. The purpose of the proposed method is generating an analog signature to provide data confidentiality and security during the data transfer, compared to the digital signature. The holographic encryption technique applied to a hash value reveals an analog-type of pseudo-random pattern in the analog signature scheme. The public key and secret key needed to verify the analog signature are computed from public key ciphers which are generated by the same holographic encryption. The proposed analog signature scheme contains a kind of double encryption in the process of generating signature and key, which enhances security level more than the digital signature. The results of performance simulations show the feasibility of the highly secure signature scheme, and security analysis shows high robustness against known-message attacks and chosen-message attacks. In addition, the proposed method can apply to one-time signature schemes which can be used to sign only one message and it can also apply to authentication, e-mails, electronic banking and electronic data interchange.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.443-446
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• 2004

Short channel IC circuits become increasingly important in modern high performance electronic systems. In this paper, parts of an analog hearing aid, an amplifier and a regulator, which are implemented with short channel CMOS devices, are designed and optimized in its performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.