• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.88-97
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• 1994

We describe the design, fabrication, and performance of the optical fiber-photodiode 1$\times$12 arry module using mesa-type InS10.53T GaS10.47TAS/INP 1$\times$12 PIN photodiode array. We fabricated the PIN PD array for high-speed optical fiber parallel data link optimizing quantum efficiency, operating speed sensitivity from the PIN-FET structure, and electrical AC crosstalk. For each element of the array, the diameter of the photodetective area is 80 $\mu$m, the diameter of the p-metal pad is 90 $\mu$m, and the photodiode seperation is 250 $\mu$m to use Si v-groove. Ground conductor line is placed around diodes and p-metal pads are formed in zigzag to reduce Ac capacitance coupling between array elements. The dark current (IS1dT) is I nA and the capacitance(CS1pDT) is 0.9 pF at -5 V. No signifcant variations of IS1dT and CPD from element to element in the array were observed. We calulated the coupling efficiency for 10/125 SMF and 50/125 GI MMF, and measured the responsivity of the PD array at the wavelength is 1.55 $\mu$ m. Responsivities are 0.93 A/W for SMF and 0.96 A/W for MMF. The optical fiber-PD array module is useful in numerous high speed digital and analog photonic system applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.41-49
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• 2004

Nonlinear distortion introduced by the optical transmitter using a direct modulation of laser diode(LD) and an indirect modulation of optical modulator can limit considerably the performance of analog optical link system such as subcarrier multiplexing system. In this paper, we have compensated the nonlinear distortion of LD and optical modulator using electrical predistorter. In the case of LD, two-tone experiments using 877.5 MHz and 882.5 MHz have shown reduction of 19 dB in third-order intermodulation product(IMP$_3$). And in the case of optical modulator, we have achieved nearly 21 dB reduction in IMP3 through two-tone experiments using 1.8975 GHz and 1.9025 GHz. The spurious free dynamic ranges of LD and optical modulator are also improved by 5 dB/Hz$^{2}$ 3/ and 7 dB/Hz$^{2}$ 3/, respectively.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.3-4
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• 2014

무선전력전송 회로는 부하의 변동에 따라 출력값을 알맞게 제어해 줄 필요가 있는데 송신부와 수신부 회로는 분리되어 있으므로 제어루프 또한 분리되어야 한다. 기존에는 주로 통신방식이나 부하측 변조를 이용한 1차측 제어를 사용하였다. 하지만 통신을 이용하는 경우 가격이 비싸고 시스템이 복잡하며, 부하측 변조 방식은 제어회로의 반응이 느리다는 단점이 있다. 본 논문은 2.5W급 전계결합형 무선전력회로에 대하여 LED 광학링크를 이용해 송신부의 스위칭 주파수를 제어하는 회로를 제안한다. 이 회로는 수신부에 포토다이오드와 연산증폭기를 내장하여 부하에 추가적인 배터리전원 없이 저가로 우수한 성능의 제어기를 구성할 수 있으며, 그 성능을 하드웨어로 검증하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.319-320
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• 2005

This paper describes the principles and structures of an expert system for arrester diagnosis. The expert system analyzes and decides the arrester condition by total leakage current, its harmonic component, and temperature because the deterioration of arresters appeared in an increase of leakage current and surface temperature of it. Additionally, influence of system voltage harmonics and ambient temperatures on leakage current changes were considered in the design. The expert system is consisted of a data acquisition module and a computer for monitoring. The acquired analog data are digitalized and transmitted to the computer by an optical link which is free from interference.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10B
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• pp.1150-1158
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• 2011

More than 100 Mbps rate is needed in the UBcN for a subscriber to receive broadband traffics with multi-channel like UDTV or 3DTV. Although the optical fiber is recently deployed for the FTTH, the UTP is the most widely used medium and will be used in UBcN age. Network providers may consider the 1000BASE-T or the vectorized VDSL if they adopts the UTP in the place where does not have optical fibers. But UTP should be expanded because 1000BASE-T and vectorized UTP needs 4 and 3 pairs cable, respectively while residential region has not exceeding 2 pair UTP cable. To solve the problem, we propose a 500BASE-T technology using 2 pairs UTP in this paper. The technology introduces a rate adaptation sublayer and a SERDES sublayer above and under the PCS, respectively. The rate adaptation sublayer is compatible for the GMII. Also, if we modify the SERDES sublayer, the technology can easily obtain 250BASE-T with 2 pairs UTP. We implement such functions with FPGA and analog board and verify the function of rate adaptation and symbol vector synchronization, and effective transmission rate by experiments. In particular, we show that link efficiency is increased by enable control in the rate adaptation sublayer.