• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.951-954
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• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.54-57
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• 2003

A new non linear, mean value, instantaneous following control technique to design half bridge converter is proposed in witch control principle uses characteristic that reset time of analog integrator is inverse proportion In input voltage. It is Important characteristic that compensation and follow-up control time are same with switching frequency. Is completed in one cycle that base control frequency. Have excellence characteristic that follow in order instruction value exactly stationary state as well as transient state. Half bridge converter that apply this control principle can know that have stabilize and excellence characteristic. This technique is verified through an experiment, and know that experiment result and theory agree well.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.26-35
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• 1997

This paper proposes a multi-bit $\Sigma\Delta$ modulator arcitecture which eliminates signal clipping problem. To avoid signal clipping, the output values of intgrators are monitored and modified by a reference value. This oepration is recorded as a digital code to restore actual signal value. Due to the digital code, the substraction of feedback value from the multi-bit quantizer can be calculated by a digital adder and this simplifies dAC operation making the accurate DAC of conventional multi-bit $\Sigma\Delta$ modulator scheme unnecessary. These features make N-th modulator can be implemented by sharing an integrator among N stages to decrease the required chip area. As an experimental example, a 4th order .sum..DELTA. modulator with oversampling ratio of 64 was simulated to show over 130 DB SNR at rail-to-rail input sinusoidal signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.114-114
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(f0= 100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPIC simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.335-337
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• 1993

Offset voltage and drift characteristics of operational amplifier are critical factor to precision AID conversion System. In this study, a method is suggested to design the programmable A/D conversion system which has high resolution and low drift characteristics. First, hardware was designed to reduce the offset voltage of integrator and comparator, and analog switches are connected to reduce the drift characteristics of operational amplifier. And then, a calibration software technique was performed to obtain the stable data from A/D converter. The main advantage of our method is high precision A/D converter can be constructed with low cost and high confidence. Therefore proposed method is expected to be used in the industrial field where a high precision measurement is required.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.470-475
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• 2002

Instantaneous following PWM control technique is pulsed nonlinear dynamic control method. This new control technique using analog integrator is proposed to control the duty ratio D of do-dc converter. In this control method, the duty ratio of a switch is exactly equal In or proportional to the control reference in the steady state or in a transient. Proposed control method compensates power source perturbation in one switching cycle, and the average value of the dynamic reference in one switching cycle. There is no steady state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with buck converter have demonstrated the robustness of the control method and verified theoretical prediction. The control method is very general and applicable to all type PWM

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.371-375
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• 1998

This paper proposes a programmable low pass filter(LPF) to estimate stator flux for speed sensorless stator flux orientation control of induction motors. The programmable LPF is developed to solve the dc drift problem associated with a pure integrator and an analog LPF with fixed pole. of the programmable LPF is located far from the origin in order to decrease the time constant as speed increases. The programmable LPF has the phase and the magnitude compensator to exactly estimate stator flux in a wide speed range. So, the drift problem is much improved and the stator flux is exactly estimated in the wide speed range. The validity of the proposed programmable LPF is verified by speed sensorless vector control of a 2.2[kW] three-phase induction motor.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.378-381
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• 2002

Instantaneous following PWM control technique is pulsed nonlinear dynamic control method. This new control technique using analog integrator is proposed to control the duty ratio D of DC-DC converter. In this control method, the duty ratio of a switch is exactly equal to or proportional to the control reference in the steady state or in a transient. Proposed control method compensates power source perturbation in one switching cycle, and the average value of the dynamic reference in one switching cycle. There is no steady state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with buck converter have demonstrated the robustness of the control method and verified theoretical prediction. The control method is very general and applicable to all type PWM.

• Journal of IKEEE
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• v.19 no.4
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• pp.479-485
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• 2015

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to $15.56{\mu}s/{\Omega}$ over the resistance deviation range of $0-200{\Omega}$ and its linearity error is less than ${\pm}0.02%$. Its temperature stability is less than $220ppm/^{\circ}C$ in the temperature range of $-25-85^{\circ}C$. Power dissipation of the converter is 60.2 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.1114-1119
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(fo=100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.