• Journal of Power Electronics
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• v.6 no.2
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• pp.139-145
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• 2006

This paper describes the ultra precise position estimation of a servomotor using a sinusoidal encoder based on Arcsine Interpolation Method for the cost reduction of circuit design. The amplitude and offset errors of the sinusoidal encoder output signals, from the encoder itself and analog signal processing procedures, are effectively compensated and on-line tuned by utilizing a low cost programmable differential amplifier without any special expensive equipment. For a theoretical evaluation of the practical resolution of this system, the relationship between the amplitude of ADC(Analog to Digital Converter) input signal errors and the anticipated resolution is also addressed. The performance of the proposed method is verified by comparing it with speed control characteristics of the servomotor driving system using a digital incremental 50,000ppr encoder in the experiments.

• Journal of Advanced Navigation Technology
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• v.23 no.4
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• pp.316-321
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• 2019

In this paper, by applying the constant current principle we develop an impedance measurement system which can measure the high precision impedance of various electric materials by using microprocessor. This measurement system board has an interface device for acquiring digital data from an external device including an impedance measuring device, and system software is also developed by a firmware program executed on such an embedded board. It can measure the high precision impedance of a specific band with 1/32768 precision by using 15-bit ADC(analog to digital converter) and calculate it to the five digits to the right of the decimal point(fraction part). Data is transmitted through a USB interface of a general computer and a measuring device to manage digital data. An impedance measurement system equipped with a communication function capable of a more general and easy-to-use interface than other equipment is developed and verified.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.96-102
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• 1998

This paper describes the design of the digital controller for Full-Bridge Phase-shifted converter with zero-voltage switching (ZVS). Although digital control techniques are widely used in the area of inverters and motor drives, their use for the control of high-frequency switching power supply is still rare. Therefore, this paper presents design method of digital controller of Full-Bridge Phase-shifted converter with zero-voltage switching (ZVS) and compares with conventional analog controller. The controller design is optimized by running computer simulation with the MATLAB numerical calculation package.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.667-670
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• 2004

In this paper, we have presented the improved IF transceiver architecture and the implementation and experimental results on re-configurable transceiver based on digital IF for multiple wideband OFDM/TDD base stations for high-speed portable internet-service in which is issued Korea. The implemented IF transceiver has been designed to support multiple frequency allocations and multiple standards by only modifying the programmable software not its hardware like as the software-defined-radio concept. Also, the digital complex quadrature modulation technique has been used for the digital IF transmitter, which is able to combine multiple frequency bands in digital processing block not RF block and to reject the image frequency signals. And the bandpass sampling technique has been used for the digital IF receiver to reduce the sampling rate of ADC. This paper has shown the experiment results on the frequency response and constellation on the base-station implemented using the modified IEEE 802.16a/e physical layer channel structure based on OFDM/TDD.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.1
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• pp.39-44
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• 2013

In this paper digital phase-shifter for multi-arm spiral antennas was designed by using Hilbert transform. All frequency components in input signal are phase-shifted for 90 degree by Hilbert transform, and the transform is implemented by FIT and IFIT. Digital phase-shifter generates two signals with phase difference of 90 degree by using Hilbert transform from input signals sampled by analog-digital converter(ADC), and then the input signal is phase-shifted for a given phase by using two signals. Hilbert transform based on digital phase-shifter is designed by Xilinx System generator, and the effects of input noise, FIT point, sampling period, initial phase of input signal, and shifted phase are simulated and its results are compared with Matlab results.

• Journal of IKEEE
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• v.17 no.3
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• pp.234-240
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• 2013

This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.2
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• pp.144-150
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• 2022

The on-board processor of satellite synthetic aperture radar(SAR) generates transmission signal by digital signal processing, converts it into an analog signal. At this time, the transmission signal generated from the baseband requires the frequency modulation to convert it to the high-frequency band in order to improve the stability. General frequency modulation method using local oscillator(LO) causes IQ imbalance due to phase error/magnitude error and these error reduce performance of SAR. To generate transmission signal without phase/magnitude error, this paper suggests design method of the frequency modulation method using digital to analog converter(DAC) at on-board SAR. For design, this paper analyzes the characteristic of DAC mode and uses pre-compensation filter. To analyze the proposed method performance, performance index are compared with IQ imbalance signals. This method is suitable for on-board SAR using fast sampling DAC and has the advantage of being able to solve IQ imbalances.

• 한국초전도학회:학술대회논문집
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• v.11
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• pp.51-51
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• 2001

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.