• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.38-46
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• 2006

A parallel analog Viterbi decoder which decodes PRML signal of DVD has been fabricated into a VLSI chip. The parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. In this paper, the analog parallel Viterbi decoding technology is applied for the PRML signal decoding of DVD. The benefits are low power consumption and less silicon consumption. The designed circuits are analysed and the test results of the fabricated chip are reported.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.135-143
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• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.

• The Journal of the Acoustical Society of Korea
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• v.16 no.2
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• pp.80-88
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• 1997

In this paper, the implementation of audio/data processor using ETRI DSP to support analog mode in digital/analog dual mode mobile phone is presented. Audio/data processor performs the wideband data processing, audio signal processing, demodulation function, and data rate conversion when it is operated in analog mode. These functions are programmed in assembly language, and then loaded to ETRI DSP together with vocoder program for the digital mode operation. This is a very efficient implementation of the dual mode cellular phone ASIC since the vocoder for the digital mode and audio/data processor for the analog mode are programmed together in the same hardware.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.485-490
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• 2004

This paper presents a new interpolation algorithm for measuring high resolution position information which is prepared to a nino servo control motor using analog quadrature encoder. In the past, there are large capacity of memory(ROM or RAM) and two high price and resolution A/D(Analog-to-Digital Converter) for sensing two quadrature signals from a analog sinusoidal encoder interpolation. But high resolution of position from sinusoidal encoder can be obtained by using only small capacity of memory, one A/D converter and comparator. Experimental results show that the proposed algorithm is useful for measuring high resolution position.

• Molecules and Cells
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• v.28 no.5
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• pp.473-477
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• 2009

Previously, the 9-mer analog peptides, 9Pbw2 and 9Pbw4, were designed based on a defensin-like peptide, protaetiamycine isolated from Protaetia brevitarsis. In this study, antifungal effects of the analog peptides were investigated. The antifungal susceptibility testing exhibited that 9Pbw4 contained more potent antifungal activities than 9Pbw2. A PI influx assay confirmed the effects of the analog peptides and demonstrated that the peptides exerted their activity by a membrane-active mechanism, in an energy-independent manner. As the noteworthy potency of 9Pbw4, the mechanism(s) of 9Pbw4 were further investigated. The membrane studies, using rhodamine-labeled giant unilamellar vesicle (GUV) and fluorescein isothiocyanate (FITC)-dextran loaded liposome, suggested that the membrane-active mechanism of 9Pbw4 could have originated from the pore-forming action and the radii of pores was presumed to be anywhere from 1.8 nm to 3.3 nm. These results were confirmed by 3D-flow cytometric contour-plot analysis. The present study suggests a potential of 9Pbw4 as a novel antifungal peptide.

• Journal of the Optical Society of Korea
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• v.19 no.3
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• pp.255-259
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• 2015

We have proposed and experimentally verified a pulse-width modulation (PWM) generator which directly generated a PWM signal in the optical domain. Output waveforms were clear at the repetition rate of 16 MHz; the duty cycle (DC) was from 14.7% to 72.1%; and the DC-control resolution was about 4.399%/dB. The PWM generator' operation principle is based on the injection-locking property of a single-mode Fabry-$P{\acute{e}}rot$ laser diode (SMFP-LD). The SMFP-LD, which has a self-locked mode wavelength at ${\lambda}_{PWM}$, was used to detect the power of the injection-locking signal (optical analog input). If the analog input power is high, the SMFP-LD is locked to the wavelength of the input signal ${\lambda}_a$ and there is no output after an optical bandpass filter (OBF). If the analog input power is low, the SMFP-LD is unlocked and there is output signal at ${\lambda}_{PWM}$ after the OBF. Thus, the SMFP-LD plus the OBF provide digital output for an analog input. The DC of the output PWM signal can be controlled by tuning the power of the analog input.

• ETRI Journal
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• v.26 no.6
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• pp.560-564
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• 2004

An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a $0.25{\mu}m$ double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.3-3
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• 2010

The Characteristics of Digital Vterbi Decoder utilizing the analog parallel processing circuit technology is proposed. The Analog parallel structure of the viterbi decoder acted by a replacement of the conventional digital viterbi Decoder is progressing fastly. The proposed circuits design han, low distortion, high accuracy over the previous implementation and dynamic programming.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.212-215
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• 2000

This paper introduces to design analog circuits with Verilog-A. It is a tool for design and simulation of analog ICs in behavioral level. Verilog-A has been already established standard and used to IP development in USA. We have proved the possibility of Verilog-A by comparing with measurement data of a fabricated 235MHz PLL circuit. This paper also describes another advantage of Verilog-A.