• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.437-438
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• 2018

본 논문은 디지털 신호에 포함되어 있는 잡음을 효과적으로 제거하기 위한 프로그램 가능한 디지털 필터를 제안한다. 이러한 필터는 Altera사의 FPGA(Field Programmable Gate Array)인 cycloneII EP2C70F89618를 이용하여 구현하였다. 데이터 신호에 포함된 잡음 제거 알고리즘을 바탕으로 한 출력 영상 신호 결과로부터 알 수 있듯이 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 다양한 잡음에 대해 잡음이 제거된 출력 영상 특성을 보임을 확인하였다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1284-1287
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• 2002

A fast algorithm for a circular pattern recognition from a binary edge image is proposed in this paper. The implementation of this algorithm onto an FPGA is designed using Verilog-HDL where a target device is Altera EPF10K100ARC240-3. For a 256 ${\times}$ 256-pixe1 binary edge image assuming a real watermelon in a greenhouse, improved circuit performance of the proposed design was confirmed.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.829-832
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• 1999

In this paper, We propose design and implementation method of Modulator for IMT-2000 over reverse link. Parameters necessary for each block use those specified in cdma2000, i.e. standard for third generation cellular mobile communication which is proposed in currently North America. As software tool for modulator design, We implemented using MAX＋PLUS II that ALTERA support. Our System is totally composed of eight block and make it possible to transmit four channels(PICH, FCH, SCH, DCCH) simultaneously. Also the system is designed to make it possible to transmit data up to maximum 384kbps.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.339-342
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• 2000

This paper presented a FPGA design of SEED, which is the Korea standard 128-bit block cipher. In this work, SEED was designed technology- independently for other applications such as ASIC or core-based designs. Hence in case of changing the target of design, it is not necessary to modify design or need only minor modification to reuse the design. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once and used sequentially. So, the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. It was confirmed that the rate of resource usage is about 80% in ALTERA 10KE and the SEED design operates in a clock frequency of 131.57 MHz and an encryption rate of 29 Mbps.

• Journal of Power Electronics
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• v.13 no.1
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• pp.104-112
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• 2013

This paper presents a comparative evaluation of various topologies for three-phase power converters using the hardware-in-the-loop (HIL) simulation technique. Various switch-mode AC-DC power converters are studied, and their performance with respect to total harmonic distortion (THD), efficiency, power factor and losses are analyzed. The HIL-simulation is implemented in an Altera Cyclone II DE2 Field Programmable Gate Array (FPGA) Board and in the Matlab/Simulink environment. A comparison of the simulation and HIL-simulation results is also provided.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1478-1482
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• 2003

In this paper. Rijndael cipher algorithm is implemented by a hardware. It was selected as the AES(Advanced Encryption Standard) by NIST. It has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clock frequency. In case of decryption, it has 363 Mbps decryption rate fu 142Mhz max clock frequency. In case of cipher core, it has 320Mbps encryptionㆍdecryption rate for 125Mhz max clock frequency.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.363-366
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• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.649-651
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• 2016

본 연구에서는 디지털 신호에 포함되어 있는 잡음을 효과적으로 제거하기 위한 방법으로 프로그램 가능한 디지털 FIR 필터를 제안한다. 이러한 필터는 Altera의 FPGA(Field Programmable Gate Array)인 cyclone II EP2C70F89618를 이용하여 설계하고 구현하였다. 데이터 신호 잡음 제거 알고리즘을 바탕으로 한 영상 신호 제거 결과는 출력 영상으로부터 알 수 있듯이 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 월등히 구분이 가능한 출력 영상 특성을 보임을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.469-471
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• 2019

본 논문은 신호에 포함되어 있는 다양한 잡음을 효과적으로 제거할 수 있는 프로그램 가능한 디지털 유한 임펄스 응답 필터를 제안한다. 이러한 필터는 복잡도 등을 고려하여 3차 회로로 설계되어 있다. Altera사의 FPGA(Field Programmable Gate Array)인 cyclone II EP2C70F89618를 이용하여 설계하였다. 신호에 포함된 미세하고 다양한 잡음을 제거하기 위한 알고리즘을 개발하였다. 이를 바탕으로 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 다양한 잡음에 대해 우수한 출력 영상을 확인하였다.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.