• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.221-225
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• 2007

We have prepared $\delta$-phase SbTe alloy with various Sb contents of 64, 72, and 76 at. % and investigated the phase change temperature, the crystal structures of $\delta$-phase SbTe alloy, and determined the ovonic threshold switching voltages with edge contact type phase transition dimensions. As a result, the crystallization temperature is slightly reduced from 126 to $122^{\circ}C$, whereas the melting temperature is not changed. The ovonic threshold switching voltage is reduced from 1.6 to 0.9 V as increasing the Sb content from 64 to 76 at. %. It is found that the reductions of crystallization temperature and the ovonic threshold switching voltage are closely related with the interplanar spacing between adjacent atomic layers and the stacking number of atomic layers in a unit cell.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.61-65
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• 2011

The capabilities of finite elements codes allow now accurate simulations of blanking processes when appropriate materials modelling are used. Over the last decade, numerous numerical studies have focused on the influence of process parameters such as punch-die clearance, tools geometry and friction on blanking force and blank profile. In this study, three dimensional finite element analysis is carried out to design a lead frame blanking die using LS-Dyna3D package. After design of the blanking die, an experiment is also carried out to investigate the characteristics of blanking for nickel alloy Alloy42, a kind of IC lead frame material. In this paper, it has been researched the investigation to examine the influence of process parameters such as clearance and air cylinder pressure on the accuracy of sheared plane. Through the experiment results, it is shown that the quality of sheared plane is less affected by clearance and air cylinder pressure.

• Journal of the Semiconductor & Display Technology
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• v.7 no.2
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• pp.1-5
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• 2008

Silicide formation process and the formation sequence were investigated in this study. It was postulated that the formation of the second silicide phase involves glass formation between the first silicide phase and Si given that a thin metal film is deposited on a Si substrate. The concentration of glass was assumed to be located where the free energy of the liquid alloy with respect to the first nucleated compound and solid Si (${\Delta}$G') is most negative. It was also mentioned that the glass concentration is close to the composition of the second phase in order to achieve the maximum energy degradation. It was shown that the minimum ${\Delta}$G' concentration can be estimated by interpolating the portion of the liquidus where the liquid alloy is in equilibrium with the two solid constituents, namely the first compound phase and Si, thereby forming a hypothetical eutectic.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• Journal of the Korean institute of surface engineering
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• v.48 no.1
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• pp.23-26
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• 2015

What causes the transformation of a solar cell is the behavior difference of thermal expansion occurred between the substrate and the layer of semiconductor used in the solar cell. Therefore, the substrate has to possess a behavior of thermal expansion that is similar with that of semiconductor layer. This study employed electroforming to manufacture Fe-Ni alloy materials of different compositions. To verify the result from a finite element analysis, a two-dimensional Mo substrate was calculated and its verification experiment was conducted. The absolute values from the finite element analysis of Mo/substrate structure and its verification experiment showed a difference. However, the size of residual stress of individual substrate compositions had a similar tendency. Two-dimensional CIGS/Mo/$SiO_2$/substrate was modeled. Looking into the residual stress of CIGS layer occurred while the temperature declined from $550^{\circ}C$ to room temperature, the smallest residual stress was found with the use of Fe-52 wt%Ni substrate material.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.276-283
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• 2017

A polysilicon-based metal-semiconductor-metal (MSM) photodetector was fabricated by means of our new methods. Its photoresponse characteristics were analyzed to see if it could be applied to a sensor system. The processes on which this study focused were an alloy-annealing process to form metal-polysilicon contacts, a post-annealing process for better light absorption of as-deposited polysilicon, and a passivation process for lowering defect density in polysilicon. When the alloy annealing was achieved at about $400^{\circ}C$, metal-polysilicon Schottky contacts sustained a stable potential barrier, decreasing the dark current. For better surface morphology of polysilicon, rapid thermal annealing (RTA) or furnace annealing at around $900^{\circ}C$ was suitable as a post-annealing process, because it supplied polysilicon layers with a smoother surface and a proper grain size for photon absorption. For the passivation of defects in polysilicon, hydrogen-ion implantation was chosen, because it is easy to implant hydrogen into the polysilicon. MSM photodetectors based on the suggested processes showed a higher sensitivity for photocurrent detection and a stable Schottky contact barrier to lower the dark current and are therefore applicable to sensor systems.

• Journal of the Korean institute of surface engineering
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• v.48 no.6
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• pp.253-259
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• 2015

The test equipment becomes more important with the development of semiconductor industry. MEMS probe is an important testing component to detect the defects from the generated electric signal when it contacts the metal pad of semiconductor devices. Ni-Pd alloy has been paid attention to as a candidate of MEMS probe material because of its high surface hardness and relatively low resistivity. In this study, electroplated Ni-Pd alloy has been prepared by using ethylene diamine as a complexing agent. Solid solution alloy coating could be formed when concentration of palladium chloride and current density were in the ranges of 1~5 mM and $0.2{\sim}1.5A/dm^2$, respectively. The increase of current density brought about an decrease in palladium content, which made both of lattice parameter and grain size smaller. As a result of grain refinement, high hardness could be obtained. However, surface cracking was observed due to residual stress when the current density was above $1.3A/dm^2$. When effects of heat treatment temperature on hardness and sheet resistance were investigated, the accompanied grain growth decreased both of them. The decrease of hardness remained stable at a temperature of $200^{\circ}C$. The sheet resistance was drastically reduced at $100^{\circ}C$. After that, it was found to become constant.

• Journal of the Korean institute of surface engineering
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• v.56 no.2
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• pp.160-168
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• 2023

Recently, investigation on metallization is a key for a stretchable display. Amorphous metal such as Ni and Zr based amorphous metal compounds are introduced for a suitable material with superelastic property under certain stress condition. However, Ni and Zr based amorphous metals have too high resistivity for a display device's interconnectors. In addition, these metals are not suitable for display process chemicals. Therefore, we choose an aluminum based amprhous metal Al-Mo as a interconnector of stretchable display. In this paper, Amorphous Forming Composition Range (AFCR) for Al-Mo alloys are calculated by Midema's model, which is between 0.1 and 0.25 molybdenum, as confirmed by X-ray diffraction (XRD). The elongation tests revealed that amorphous Al-20Mo alloy thin films exhibit superior stretchability compared to pure Al thin films, with significantly less increase in resistivity at a 10% strain. This excellent resistance to hillock formation in the Al20Mo alloy is attributed to the recessed diffusion of aluminum atoms in the amorphous phase, rather than in the crystalline phase, as well as stress distribution and relaxation in the aluminum alloy. Furthermore, according to the AES depth profile analysis, the amorphous Al-Mo alloys are completely compatible with existing etching processes. The alloys exhibit fast etch rates, with a reasonable oxide layer thickness of 10 nm, and there is no diffusion of oxides in the matrix. This compatibility with existing etching processes is an important advantage for the industrial production of stretchable displays.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• Journal of the Semiconductor & Display Technology
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• v.14 no.1
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• pp.67-71
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• 2015

Pulse electroplating was studied to form nanocrystal structure effectively by changing plating current density and duty cycle. When both of plating current density and duty cycle were decreased from $100mA/cm^2$ and 70% to $50mA/cm^2$ and 30%, the P content in the Ni matrix was increased almost up to the composition of $Ni_3P$ compound and the grain growth after annealing was retarded as well. The as-plated hardness values ranging from 660 to 753 HV are mainly based on the formation of nanocrystal structure. On the other hand, the post-anneal hardness values ranging from 898 to 1045 HV, which are comparable to the hardness of hard Cr, are coming from how competition worked between the precipitation of $Ni_3P$ and the grain coarsening. According to the ANOVA and regression analysis, the plating current density showed more strong effect on nanocrystal size and film hardness than the duty cycle.