• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1535-1537
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• 2009

High performance resistive type touch panel was fabricated on flexible polyethylene terephthalate (PET) substrates coated with Al- and Ga-codoped ZnO (AGZO) films. The AGZO films were deposited by roll-to-roll direct current magnetron sputter at room temperature. The AGZO thin films on PET substrates showed high transparency (> 85 % at 550 nm) and low sheet resistance (450 ${\Omega}$/sq.). These values were similar to those of commercial ITO films used for resistive type touch panel.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.889-892
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• 2009

We have developed a practical printing technology for the gate electrode of organic thin film transistors(OTFTs) by combining screen-printing with wet-etching process using nano-silver ink as a conducting material. The screen-printed and wet-etched Ag electrode exhibited a minimum line width of ~5 um, the thickness of ~65 nm, and a resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, producing good geometrical and electrical characteristics for gate electrode. The OTFTs with the screen-printed and wet-etched Ag electrode produced the saturation mobility of $0.13cm^2$/Vs and current on/off ratio of $1.79{\times}10^6$, being comparable to those of OTFT with the thermally evaporated Al gate electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.90-93
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• 1997

고주파 반응성 스퍼터링 방법을 사용하여 희토류가 첨가된 SiO$_2$ 박막을 제작하여 특성을 조사하여, 양질의 희토류 원소가 첨가된 SiO$_2$ 박막의 최적의 제작조건을 도출하고 Er-Al:SiO$_2$ 박막의 소자웅용 가능성에 대하여 조사하였다 열처리전의 Er의 농도는 EDS(Energy dispersing x-ray spectrometer)로 측정한 결과 0.77% 로 농도를 나타내었고 코아층 첨가된 Er은 균일하게 분포되었다 크레드층의 굴절률은 633nm의 파장에서 측정하였을때 1.458이였고 코아층의 굴절률은 동일 파장에서 1.757이였다. 굴절률 분포도 (Refractive Index Profile)는 계단형 굴절률 분포로 코아층/클래드 굴절률 차 $\Delta$n$_{ESI}$ = 0.1였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.622-626
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• 2003

We report the electrical properties of organic light emitting diodes (OLEDs) depending on the crystal structure of hole injection layer of copper(II)-phthalocyanine(CuPc) and the light irradiation the carrier mobility of copper(II)-phthalocyanine(CuPc) of light source. OLEDs were constructed with indium tin oxide(ITO)/CuPc/triphenyl-diamin(TPD)/tris-(8-hydroxyquinoline)aluminum(Alq$_3$)/Al.Photocurrent multiplication of OLEDs was varied by the heat-treatment condition of CuPc thin film and the light irradiation.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.37-38
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• 2011

알루미늄은 높은 내부식성과 우수한 물리적 특성으로 철강 제품의 부식방지를 위한 표면처리와 항공 우주분야 소재로 각광을 받아왔다. 알루미늄을 철강 제품의 부식방지를 위한 표면처리 소재로 사용되는 경우 비교적 두껍게(15 ${\mu}m$ 이상) 코팅된다. 본 연구에서는 얇은 두께(3 ${\mu}m$ 이하)의 알루미늄 박막을 이용하여 높은 내식성을 갖는 코팅 공정을 개발하고자 한다. 물리기상증착으로 코팅되는 대부분의 금속은 주상정 구조를 갖는다. 주상정 구조는 grain boundary에 공극이 존재하고, 이 공극을 통해서 부식을 일으키는 물질이 보호막과 모재의 계면으로 침투하여 모재가 부식을 일으킨다. 스퍼터링 공정을 제어하여 알루미늄 박막의 공극 발생을 억제하여 보호막으로서의 기능을 향상할 수 있는 방법을 제안한다. 알루미늄 코팅을 위해서 magnetron sputtering을 이용하였으며, 기판은 냉연강판을 사용하였다. 냉연강판위에 코팅된 알루미늄 박막을 분석한 결과, 스퍼터링 소스에 역방향 자기장을 인가하여 코팅한 알루미늄 박막이 염수분무 120 시간 후에도 적청이 발생하지 않는 우수한 내식성을 보였다.

• Journal of Integrative Natural Science
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• v.2 no.4
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• pp.289-292
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• 2009

Perchlorosilanes are useful precursors for the synthesis of hydrosilanes for the fabrication of electronic devices such as silicon thin-film transistors and silicon nanoparticles. For this solution process, requirements of precursors applicable to solution process are relatively low volatile and soluble in common organic solvents. In this work, the decaphenylcyclopentasilane has been obtained from the reaction of the lithium wire and dichlorodiphenylsilane. The reaction of decaphenylcyclopentasilane with lewis acid catalyst, HCl/$AlCl_3$, gives the perchlorocyclopentasilane. Decaphenylcyclopentasilane exhibits an unusual optical property. Its optical property was characterized by UV-vis and fluorescence spectroscopy. Absorption wavelength maxima for the decaphenylcyclopentasilane was 272 nm. Decaphenylcyclopentasilane displayed an emission band at 741 nm with excitation wavelength of 272 nm.

• Journal of the Semiconductor & Display Technology
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• v.9 no.3
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• pp.75-78
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• 2010

In this study we investigated the electrical properties of ZnO-based MOS capacitor with $HfO_2$ as the gate dielectric. MIM capacitor, which uses either $HfO_2$ or $Al_2O_3$ as the dielectric layer, is also studied to understand the dependency of the dielectrics on the preparation conditions. It was found that thinner $HfO_2$ films yield better electrical properties, namely lower leakage current and higher breakdown electric field. These properties were observed to deteriorate when subsequently annealed. Capacitance in the depletion region of MOS capacitor was found to increase with UV ozone treatment time up to 60min. However, when the treatment time was extended to 120min, the trend is reversed. The 'threshold voltage' was also observed to positively shift with UV ozone treatment time up to 60min. The shift apparently saturated for longer treatment.

• Korean Journal of Optics and Photonics
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• v.18 no.5
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• pp.351-361
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• 2007

The samples composed of a GST thin film and the protective layers of $ZnS-SiO_2$ or $Al_2O_3$ coated on c-Si substrate were prepared by using the magnetron sputtering method. Samples of three different structures were prepared, that is, i) the GST single film on c-Si substrate, ii) the GST film sandwiched by the protective $ZnS-SiO_2$ layers on c-Si substrate, and iii) the GST film sandwiched by $Al_2O_3$ protective layers on c-Si substrate. The ellipsometric constants in the temperature range from room temperature to $700^{\circ}C$ were obtained by using the in-situ ellipsometer equipped with a conventional heating chamber. The measured ellipsometric constants show strong variations versus temperature. The variation of ellipsometric constants at the temperature region higher than $300^{\circ}C$ shows different behaviors as the ambient medium is changed from in air to in vacuum or the protective layers are changed from $ZnS-SiO_2$ to $Al_2O_3$. Since the long heating time of 1-2 hours is believed to be the origin of the high temperature variation of ellipsometric constants upon the heating environment and the protective layers, a PRAM (Phase-Change Random Access Memory) recorder is introduced to reduce the heating time drastically. By using the PRAM recorder, the GST samples are heated up to $700^{\circ}C$ decomposed preventing its partial evaporation or chemical reactions with adjacent protective layers. The surface image obtained by SEM and the surface micro-roughness verified by AFM also confirmed that samples prepared by the PRAM recorder have smoother surface than the samples prepared by using the conventional heater.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.327.1-327.1
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• 2014

Nitrides-on-silicon structures are considered to be an excellent candidate for unique design architectures and creating devices for high-power applications. Therefore, a lot of effort has been concentrating on growing high-quality III-nitrides on Si substrates, mostly Si(111) and Si(001) substrates. However, there are several fundamental problems in the growth of nitride compound semiconductors on silicon. First, the large difference in lattice constants and thermal expansion coefficients will lead to misfit dislocation and stress in the epitaxial films. Second, the growth of polar compounds on a non-polar substrate can lead to antiphase domains or other defective structures. Even though the lattice mismatches are reached to 16.9 % to GaN and 19 % to AlN and a number of dislocations are originated, Si(111) has been selected as the substrate for the epitaxial growth of nitrides because it is always favored due to its three-fold symmetry at the surface, which gives a good rotational matching for the six-fold symmetry of the wurtzite structure of nitrides. Also, Si(001) has been used for the growth of nitrides due to a possible integration of nitride devices with silicon technology despite a four-fold symmetry and a surface reconstruction. Moreover, Si(110), one of surface orientations used in the silicon technology, begins to attract attention as a substrate for the epitaxial growth of nitrides due to an interesting interface structure. In this system, the close lattice match along the [-1100]AlN/[001]Si direction promotes the faster growth along a particular crystal orientation. However, there are insufficient until now on the studies for the growth of nitride compound semiconductors on Si(110) substrate from a microstructural point of view. In this work, the microstructural properties of nitride thin layers grown on Si(110) have been characterized using various TEM techniques. The main purpose of this study was to understand the atomic structure and the strain behavior of III-nitrides grown on Si(110) substrate by molecular beam epitaxy (MBE). Insight gained at the microscopic level regarding how thin layer grows at the interface is essential for the growth of high quality thin films for various applications.