• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of information and communication convergence engineering
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• v.12 no.4
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• pp.252-256
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• 2014

Traditional block cipher Advanced Encryption Standard (AES) is widely used in the field of network security, but it has high overhead on each operation. In the 15th international workshop on information security applications, a novel lightweight and low-power encryption algorithm named low-power encryption algorithm (LEA) was released. This algorithm has certain useful features for hardware and software implementations, that is, simple addition, rotation, exclusive-or (ARX) operations, non-Substitute-BOX architecture, and 32-bit word size. In this study, we further improve the LEA encryptions for cloud computing. The Web-based implementations include JavaScript and assembly codes. Unlike normal implementation, JavaScript does not support unsigned integer and rotation operations; therefore, we present several techniques for resolving this issue. Furthermore, the proposed method yields a speed-optimized result and shows high performance enhancements. Each implementation is tested using various Web browsers, such as Google Chrome, Internet Explorer, and Mozilla Firefox, and on various devices including personal computers and mobile devices. These results extend the use of LEA encryption to any circumstance.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.934-936
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• 2004

본 논문의 목적은 AES(Advanced Encryption Standard)로 선정된 Rijndael 암호 및 복호 알고리즘을 하드웨어로 설계하고 이를 저비용의 FPGA로 구현하는 것이다. 설계된 AES 암호프로세서는 20만 게이트 급 이하의 FPGA로 구현한다는 비용의 제약 조건 하에서 대용량의 데이터를 암호화, 복호화 하기에 적합한 성능을 가지도록 하였다. 또한 구현 단계에서는 설계한 AES 암호프로세서와 UART 모듈을 동일 FPGA상에서 통합하여 실용성 및 면적 효율성을 보였다. 구현된 Rijndael 암호 프로세서는 20만 게이트를 갖는 Xilinx사의 Spartan-II 계열의 XC2S200 칩 사용시 53%의 면적을 차지하였고, Static Timing Analyzer로 분석한 결과 최대 29.3MHz 클럭에서 동작할 수 있고 337Mbps의 최대 성능을 가진다. 구현된 회로는 실제 FPGA를 이용하여 검증을 수행하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.05a
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• pp.125-128
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• 2019

최근 사물인터넷 기술의 발전과 함께 하드웨어 디바이스에서 측정하는 센싱 데이터를 보호하기 위해 다양한 방식의 암호화 알고리즘을 채택하고 있다. 그 중 전 세계에서 가장 많이 사용하는 암호화 알고리즘인 AES(Advanced Encryption Standard) 또한 강력한 안전성을 바탕으로 많은 디바이스에서 사용되고 있다. 하지만 AES 알고리즘은 DPA(Differential Power Analysis), CPA(Correlation Power Analysis) 같은 부채널 분석 공격에 취약하다는 점이 발견되었다. 본 논문에서는 부채널 분석 공격대응방법 중 가장 널리 알려진 마스킹 기법을 적용한 AES 알고리즘의 소프트웨어 최적화 구현 기법을 제시한다.

• Journal of KIISE
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• v.42 no.9
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• pp.1100-1108
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• 2015

Classes.dex, which is the executable file for android operation system, has Java bite code format, so that anyone can analyze and modify its source codes by using reverse engineering. Due to this characteristic, many android applications using classes.dex as executable file have been illegally copied and distributed, causing damage to the developers and software industry. To tackle such ill-intended behavior, this paper proposes a technique to encrypt classes.dex file using an AES(Advanced Encryption Standard) encryption algorithm and decrypts the applications encrypted in such a manner in order to prevent reverse engineering of the applications. To reinforce the file against reverse engineering attack, hash values that are obtained from substituting a hash equation through the combination of salt values, are used for the keys for encrypting and decrypting classes.dex. The experiments demonstrated that the proposed technique is effective in preventing the illegal duplication of classes.dex-based android applications and reverse engineering attack. As a result, the proposed technique can protect the source of an application and also prevent the spreading of malicious codes due to repackaging attack.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.1
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• pp.296-308
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• 2015

Advanced Encryption Standard (AES) is widely used for protecting wireless sensor network (WSN). At the Workshop on Cryptographic Hardware and Embedded Systems (CHES) 2012, G$\acute{e}$rard et al. proposed an optimized collision attack and break a practical implementation of AES. However, the attack needs at least 256 averaged power traces and has a high computational complexity because of its byte wise operation. In this paper, we propose a novel double sieve collision attack based on bitwise collision detection, and an improved version with an error-tolerant mechanism. Practical attacks are successfully conducted on a software implementation of AES in a low-power chip which can be used in wireless sensor node. Simulation results show that our attack needs 90% less time than the work published by G$\acute{e}$rard et al. to reach a success rate of 0.9.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.717-726
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• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• Journal of information and communication convergence engineering
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• v.10 no.3
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• pp.248-252
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• 2012

The sensor network standard DASH7 was proposed to improve transmission quality and low power communication. Specifications for the standard are currently being developed, so the security specification has not been firmly implemented. However, without a security specification, a network cannot work due to threats from malicious users. Thus we must ensure confidentiality and authentication of data packets by using a cryptography method. To contribute to the DASH7 security specification, this paper shows the implementation results of network and data link layer security by using advanced encryption standard (AES) counter with CBC-MAC (CCM) over CC430 sensor nodes.

• Review of KIISC
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• v.14 no.3
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• pp.36-48
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• 2004

네트워크 기술의 발전으로 사회 여러 분야에서 인터넷을 이용하여 다양한 서비스들이 제공되고 있다. 이러한 서비스가 널리 확산됨에 따라 인터넷 상에서 전송되는 정보의 기밀성과 무결성을 보장하기 위한 암호 기술이 크게 주목을 받고 있다. 현재 널리 사용되고 있는 암호 알고리즘으로는 FIPS 197(Federal Information Processing Standard)에서 정의한 AES(Advanced Encryption Standard)와 FIPS 46-3에 채택된 Triple DES(Data Encryption Standard), FIPS 198에 정의된 HMAC 등이 있다. 이러한 알고리즘들은 시스템 사이의 상호 운용을 위해 제정되었으며, 공유 키 재료(Shared keying material) 설정이 사전에 이뤄져야 한다. 키 재료의 설정은 신뢰기관에 의해 분배가 가능하나, 객체의 수가 증가함에 따라 키 재료 분배 작업이 지수적으로 증가하게 되는 문제점이 있다. 그러므로, 본고에서는 이러한 키 재료 분배의 문제점과 효율적인 키 설정 스킴에 대하여 기술하고 있는 NIST 800-56을 분석하고자 한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.1-6
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• 2022

In this paper, the design of lightweight S-Box structure for implementing a low power AES cryptosystem based on composite field. In this approach, the S-Box is designed as a simple structure by which the three modules of x², λ, and GF((2²)²) merge into one module for improving the usable area and processing speed on GF(((2²)²)²). The designed AES S-Box is modelled in Veilog-HDL at structural level, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool, where Spartan 3s1500l is used as a target FPGA device. It is shown that the designed S-Box is correctly operated through simulation result, where ModelSim 10.3. is used for performing timing simulation.