• 한국전자거래학회지
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• 제15권4호
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• pp.21-31
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• 2010

최근 모바일 컴퓨터를 사용한 온라인 금융 거래, 온라인 쇼핑과 같은 e-비즈니스가 널리 확산되고 있다. 대부분의 모바일 컴퓨터는 데이터 저장을 위해 NAND 플래시 메모리 기반의 저장장치를 사용한다. 플래시 메모리 저장장치는 그 내부에 Flash Translation Layer(FTL)이라는 소프트웨어가 사용되고 있다. FTL은 파일 시스템으로부터 요청되는 논리 주소를 플래시 메모리의 물리 주소로 변환하며 이를 위하여 사상 테이블을 사용한다. 기존 FTL은 매우 큰 주소 사상 테이블을 RAM에 유지해야 하는 문제점을 가지고 있다. 이를 해결하기 위하여 본 논문에서는 새로운 사상 테이블의 캐싱 기법을 제안하였다. 트레이스 기반의 시뮬레이션을 통해 제안한 사상 테이블 캐싱 기법은 공간 비용을 대폭 줄이고 시간 비용은 크게 증가하지 않음을 알 수 있었다. 특히, e-비즈니스 환경의 온라인 트랜잭션 워크로드에서 많은 공간 비용 절감 효과를 보였다.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.71-78
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• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.

• ETRI Journal
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• 제30권6호
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.243-245
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• 2004

This paper proposes design and implementation for Seamless Handoff method between adapters in a system environment where both wired and wireless adapters are present First of all, by settingLayer 2 address of wired adapter to Layer 2address of wireless adapter, then generate virtual adapter on the above layer to make these two adapters operate on an IP address. Under the condition, when wired communication via the wired adapter gets disconnected while in service, wireless handoff occurs by mapping information on the wireless adapter to the virtual adapter. According to the method proposed in this paper, continuous session can be obtained even when handoff between wired and wireless adapters occurs at lower level in an application where both IP address and Port address are used to maintain session since If address does not change.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2016년도 추계학술발표대회
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• pp.234-237
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• 2016

Address Resolution Protocol (ARP) is used for mapping a network address to physical address in many network technologies. However, since ARP protocol has no security feature, it always abused by attackers for performing ARP-based attacks. Researchers presented many technologies to improve ARP protocol, but most of them require a high implementation cost or scarify the network performance for using ARP protocol securely. In this paper, we present an ARP-disabled network system to neutralize the ARP-based attacks. "ARP-disabled" means suppress the ARP messages like request, response and broadcast messages, but not the ARP table. In our system, ARP tables are used for managing static ARP entries without prior knowledge (e.g. IP, MAC list of client devices). This is possible because the MAC address was designed to be derived from IP address. In general, our system is safe from the ARP-based attacks even the attacker has a strong power. Moreover, we saved network bandwidth by disabling the ARP messages.

• 한국컴퓨터정보학회논문지
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• 제22권12호
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 컴퓨터소사이어티 추계학술대회논문집
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• 한국정보과학회논문지:시스템및이론
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• 제37권2호
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• pp.90-102
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• 2010

플래시 메모리는 저전력, 비휘발성, 충격 내구성의 특성 때문에 임베디드 시스템에서 가장 중요한 저장 장치로 사용되고 있다. 하지만, 플래시 메모리는 덮어쓰기가 안 되는 제약 때문에 FTL이라고 하는 주소 변환을 위한 소프트웨어를 사용하며, 효율적인 주소변환을 위해서 로그 버퍼 기반의 FTL이 많이 사용되고 있다. 로그 버퍼 기반 FTL의 설계시에 중요한 사항으로서 데이터 블록과 로그 블록의 연관구조를 결정하는 문제가 있다. 기존의 기법들은 설계시에 결정된 정적인 구조를 사용하지만, 본 논문에서 는 어플리케이션의 시간적 공간적 워크로드의 변화를 고려한 적응적 로그 블록 연관 구조를 제안한다. 제안하는 FTL은 실행시간에 어플리케이션의 워크로드의 변화에 최적화된 로그 블록 연관 구조를 사용함으로써 정적으로 최적의 연관 구조를 선택하는 기존의 기법 대비 5~16%의 성능 향상을 가져왔다.

• 한국컴퓨터정보학회논문지
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• 제24권8호
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• pp.9-17
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• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• 한국지능정보시스템학회:학술대회논문집
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• 한국지능정보시스템학회 2005년도 공동추계학술대회
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• pp.295-303
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• 2005

Semantic Web and its related technologies have been opening the era of information sharing via Web. In the meantime, there are several huddles to overcome toward the new era and one of the major huddles is information integration issue unless we build and use a single unified but huge ontology which address everything in the world. Particularly in e-business area, information integration problem must be a great concern in search and comparison of products from various internet shopping sites and e-marketplaces. To overcome such an information integration problem, we propose an ontology driven mapping algorithm between heterogeneous product classification and description frameworks. We also perform comparative evaluation of the proposed mapping algorithm against a well-known ontology mapping tool, PROMPT.