• Journal of the Korean Geophysical Society
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• v.4 no.4
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• pp.239-249
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• 2001

NAT (Network Address Translation) is an IP address modification protocol that translates private IP addresses into authentic Internet addresses. The main features of NAT are to improve network security and to save IP addresses. Generally speaking, in order to perform its functionality. NAT uses the address informaiton in the packet header. Certain application protocols, however, use the information in the packet data as well as the imformation in the packet header to perform end-to-end communication. Therefor, to support these types of application protocols, NAT should be able to perform appropriate translation of protocol information in the packet data. In this thesis, we design and implement a method which translates virtual IP information in the packet data into real IP information by using port proxy server.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2637-2640
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• 2003

In this paper, we propose a simple and efficient data input/output block with high speed between Motorola MPC8XX microprocessor and memory devices. Proposed method is capable of high speed data read and write using the address decoder and the burst cycle between Motorola PowerPC based MPC8XX microprocessor and fixed address locating memory devices such as FIFO, PCMCIA card, and so on. Experimental results are given our findings and discussions.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.924-927
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• 2003

In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.992-1001
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• 1996

Radix sort scans the data twice in a pass, to search bit 0s of the items being sorted and store them into the lowest address, and to search bit 1s and st ore them into the following addresses. This doubles the sorting time. In this paper, we introduce Reverse Radix Sort Algorithm, in which the data being sorted are sacnned just once and write upward from the lowest address if it is 0 and downward from the highest address if it is 1. The algorithm is simple and the hardware sorter implemented by this method shows very high sorting sped. Hardware implementation requires two separate pocket memories, register, an upward increasing address counter, a downward decreasing address counter, and comparator. The software simulation of Reverse Radix Sor Algorithm performs sorting in the speed of 54.9ms per 10 thousand of 8 bit digit data, but the hardware sorter spends 5.3ms to sort the same number of data.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.35-40
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• 2009

Many researchers strive to research on ways on how to improve the performance of RFID system and many papers were written to solve one of the major drawbacks of potent technology related with data management. As RFID system captures billions of data, problems arising from dirty data and large volume of data causes uproar in the RFID community those researchers are finding ways on how to address this issue. Especially, effective data management is important to manage large volume of data. Data reduction techniques in attempts to address the issues on data are also presented in this paper. This paper introduces readers to a new data reduction algorithm that might be an alternative to reduce data in RFID Systems. A process on how to extract data from the reduced database is also presented. Performance study is conducted to analyze the new data reduction algorithm. Our performance analysis shows the utility and feasibility of our categorization reduction algorithms.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.49-56
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• 2016

Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.571-575
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• 2004

Having age of ubiquitous ahead, existing IPv4's address space insufficiency phenomenon appears because of increasing network usage as well as multimedia data transmission becomes much, necessity of new IP address system that guarantee QoS are needed. IPv6 was made to solve these problem. IPv6 solves address space insufficiency phenomenon offering by 128bit address space, and also offers hierarchical address layer that support improved QoS. IPv6 defines relation between surrounding node using Neighbor Discovery protocol. Used Neighbor Discovery messages, grasp surrounding node, include important informations about network. These network information outcrops can give rise in network attack and also service that use network will paralysis. Various kinds of security limitation was found in Present Neighbor Discovery protocol therefore security function to supplement tris problem was required. In this thesis, Secure Neighbor Discovery protocol that add with security function was design and embody by CGA module and SEND module.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.235-238
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• 2002

This paper proposes a novel scheme of designating non-cacheable addresses of memories in embedded systems of multi-master architectures without a Memory Management Unit (MMU). As a solution for data coherency problem between external memories and a cache memory, we proposes a cache masking scheme by allocating the most significant bit of address not used in 32-bit address system as indicator bit to designate non-cacheable address. As this scheme enables non-cacheable area designation every address, the simpler in the aspect of hardware and more flexible size of non-cacheable area can be obtained.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2061-2068
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• 2016

A Bloom filter is a space-efficient data structure popularly applied in many network algorithms. This paper proposes a vectored Bloom filter to provide a high-speed Internet protocol (IP) address lookup. While each hash index for a Bloom filter indicates one bit, which is used to identify the membership of the input, each index of the proposed vectored Bloom filter indicates a vector which is used to represent the membership and the output port for the input. Hence the proposed Bloom filter can complete the IP address lookup without accessing an off-chip hash table for most cases. Simulation results show that with a reasonable sized Bloom filter that can be stored using an on-chip memory, an IP address lookup can be performed with less than 0.0003 off-chip accesses on average in our proposed architecture.