• Nuclear Engineering and Technology
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• v.48 no.4
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• Nuclear Engineering and Technology
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• v.52 no.11
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• pp.2535-2542
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• 2020

To understand the fundamental parameters of Alvand tokamak, A Rogowski coil with an active integrator was designed and constructed. Considering the characteristics of the Alvand tokamak, the structural and electrical parameters affecting the sensor function, were designed. Calibration was performed directly in the presence of plasma. The sensor has a high resistance against interference of external magnetic fields. Plasma current was measured in various experiments. Based on the plasma current profile and loop voltage signal, the time evolution of plasma discharge was investigated and plasma behavior was analyzed. Alvand tokamak discharge was divided into several regions that represents different physical phenomena in the plasma. During the plasma discharge time, plasma had significant changes and its characteristic was not uniform. To understand the plasma behavior in each of the phases, the Rogowski sensor should have sufficient time resolution. The Rogowski sensor with a frequency up to 15 kHz was appropriate for this purpose.

• Corrosion Science and Technology
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• v.10 no.4
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• pp.125-130
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• 2011

This study was performed to improve the corrosion resistance and the stability of passive film on copper tube by potentiostatic polarization method in synthetic tap water. Formation of passive film was carried out by anodic potentiostatic polarization at various passivation potentials and passivation times in 0.1 M NaOH solution. Stability of passive film and corrosion resistance was evaluated by self-activation time, ${\tau}_0$ from passive state to active state on open-circuit state in 0.1 M NaOH solution. Addition of polyphosphate in NaOH solution prolonged the self-activation time and improved the corrosion resistance, and the addition of 5 ppm polyphosphate was most effective. It was also observed that better corrosion resistance was obtained by potentiostatic polarization at 1.0 V (vs. SCE) than at any other passivation potentials. Passivated copper tube showed perfect corrosion resistance for the immersion test in synthetic tap water showing that the anodic potentiostatic polarization treatment in 0.1 M NaOH with 5 ppm polyphosphate solution would be effective in improving the corrosion resistance and preventing the blue water problem.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.635-636
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• 2006

A self-biased CMOS current reference is described which provides supply and temperature independent bias current. The supply independency is obtained by subtracting two bias currents which have the same supply dependency. Unlike the conventional self-bias CMOS current reference, excellent supply independency can be obtained even with the minimum channel length devices and thus smaller area implementation becomes possible. The supply independent bias current is then applied to a temperature compensating circuit and as a result supply and temperature independent bias current is obtained. The current reference has been implemented in a $0.25{\mu}m$ standard CMOS technology. The active silicon area is only $45{\mu}m{\times}45{\mu}m$. The simulated temperature coefficient is 64ppm/$^{\circ}C$ in temperature range between $0^{\circ}C$ and $120^{\circ}C$. Supply voltage can be as low as 1.3V and the supply dependency of the current reference is measured to be smaller than 4500ppm/V. While providing $10.25{\mu}A$ output current, the current reference consumes $160{\mu}W$.

• Journal of the Korean Electrochemical Society
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• v.1 no.1
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• pp.8-13
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• 1998

This work presents the way how to evaluate the degree of reversibility of the discharging process undergone by the nickel hydroxide film cathodically deposited on pure nickel as a positive electrode for electrochemical capacitor using the combined cyclic voltammetry and potential drop method, supplemented by galvanostatic discharge and open-circuit potential transient methods. The time interval necessary just to establish the current reversal of anodic to cathodic direction from the moment just after applying the potential inversion of anodic to cathodic direction, was obtained on cyclic voltammogram. The cathodic charge density passed upon dropping the applied potential, was calculated on potentiostatic current density-time curve. Both the time interval and the cathodic charge density in magnitude can be regarded as being measures of the degree of reversibility of the discharging process undergone by the positive active material for supercapacitor, i.e. , the longer the time interval is, the lower is the degree of reversibility and the greater the cathodic charge density is, the higher is the degree of reversibility. From the applied potential dependences of the time interval and cathodic charge density, discharge at $0.42 V_{SCE}$ was determined to be the most reversible.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.561-568
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• 2011

This paper describes the operation characteristic of a single-phase PFC converter with 1-switch voltage doubler strategy for single-phase double-conversion UPS. A single-phase PFC converter with 1-switch voltage doubler strategy needs a diode bridge and one bidirectional active switch. Thus it is possible to reduce the material cost. However, the study results of operation characteristic and controller design has not been known after the converter circuit was proposed. For the performance evaluation of PFC converter, single-phase 3kVA double-conversion UPS was tested. The performance of PFC converter is experimentally confirmed with followings - input current reference traking, input power factor correction.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.1
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• pp.1-7
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• 2012

This paper describes the performance comparison results for current controller of a single-phase PFC converter with 1-switch voltage doubler strategy for single-phase double-conversion UPS(Uninterruptible Power Supply). A single-phase PFC converter with 1-switch voltage doubler strategy needs a diode bridge and one bidirectional active switch. Thus it is possible to reduce the material cost. However, the study results of current controller design and comparison of current control method has not been known after the converter circuit was proposed. For the performance comparison of current control, single-phase 3 kVA double-conversion UPS was tested. The performance of PI and PR current controller is experimentally confirmed with followings - input current reference tracking, input power factor correction and input current THD suppression.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.165-166
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• 2013

기존의 위상천이 풀 브리지 DC/DC 컨버터의 경우 변압기의 누설 인덕턴스와 정류 스위치의 기생 출력 캐패시턴스 사이의 공진으로 인하여 정류 스위치에 스파이크 전압이 발생하며, 이는 시스템의 전력 변환 효율을 감소시킨다. 최근에 보조 DC/DC 컨버터를 사용하여 클램핑 캐패시터에서 흡수된 에너지를 부하로 회기시키는 방법이 연구되고 있으나, 보조 DC/DC 컨버터를 설계하기 위한 정확한 분석은 제시되지 않았다. 따라서, 본 논문에서는 2차 측 정류기의 공진 전압을 저감할 수 있는 비동기식 능동형 스너버 회로의 설계방법을 제안한다. 또한, 초기 기동 시에 발생되는 큰 공진에너지를 히스테리시스 회로를 이용하여 저항을 통해 소모시킴으로써 보조 DC/DC 컨버터의 자성소자를 최소화할 수 있다. 본 논문에서는 제안된 방식의 타당성을 검증하기 위하여 이론적으로 분석하며, 450W급 시작품을 제작하여 제안방식의 타당성을 검증하였다.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.