• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39B no.7
• /
• pp.440-448
• /
• 2014

A $4{\times}10$ Gb/s Transimpedance Amplifier (TIA) array is implemented in $0.13{\mu}m$ CMOS process technology, which will be used in the receiver of TWDM-PON system. A technology for bandwidth enhancement of a given $4{\times}10$ Gb/s TIA presented under inductor peaking technology and a single 1.2V power supply based low voltage design technology. It achieves 3 dB bandwidth of 7 GHz in the presence of a 0.5 pF photodiode capacitance. The trans-resistance gain is $50dB{\Omega}$, while 48 mW/ 1channel from a 1.2 V supply. The input sensitivity of the TIA is -27 dBm. The chip size is $1.9mm{\times}2.2mm$.

• Journal of Educational Research in Mathematics
• /
• v.24 no.3
• /
• pp.387-407
• /
• 2014

This study investigeted secondary math teachers' difficulties of technology in geometry class with grounded theory by Strauss and Corbin. 178 secondary math teachers attending the professional development program on technology-based geometry teaching at eight locations in January 2014, participated in this study with informed consents. Data was collected with an open-ended questionnaire survey. In line with grounded theory, open, axial and selective coding were applied to data analysis. According to the results of this study, teachers were found to experience resistance in using technology due to new learning and changes, with knowledge and awareness of technology effectively interacting to lessen such resistance. In using technology, teachers were found to go through the 'access-resistance-unaccepted use-acceptance' stages. Teachers having difficulties in using technology included the following four types: 'inaccessible, denial of acceptance, discontinuation of use, and acceptance 'These findings suggest novel perspectives towards teachers having difficulties in using technology, providing implications for teachers' professional development.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.1
• /
• pp.443-450
• /
• 2017

Nowadays, Power Line Communication (PLC) is gaining high attention from industry and electric supply companies for the services like demand response, demand side management and Advanced Metering Infrastructure (AMI). The reliable services to consumers using PLC can be provided by utilizing an efficient PLC channel for which sophisticated channel modeling is very important. This paper presents characterization of a Low Voltage (LV) access network for Narrowband Power Line Communications (NB-PLC) using transmission line (TL) theory and a Simulink model. The TL theory analysis not only includes the constant parameters but frequency selectivity is also introduced in these parameters such as resistance, conductance and impedances. However, the proposed Simulink channel model offers an analysis and characterization of capacitive coupler, network impedance and channel transfer function for NB-PLC. Analysis of analytical and simulated results shows a close agreement of the channel transfer function. In the absence of a standardized NBPLC channel model, this research work can prove significant in improving the efficiency and accuracy of NB-PLC communication transceivers for Smart Grid communications.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2011.05a
• /
• pp.28.2-28.2
• /
• 2011

Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

• Journal of Advanced Marine Engineering and Technology
• /
• v.29 no.6
• /
• pp.707-712
• /
• 2005

PRAM (Phase change random access memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change materials have been researched in the field of optical data storage media. Among the phase change materials. $Ge_2Sb_2Te_5$ is very well known for its high optical contrast in the state of amorphous and crystalline. However the characteristics required in solid state memory are quite different from optical ones. In this study. the structural Properties of GeSbTe thin films with composition were investigated for PRAM. The 100-nm thick $Ge_2Sb_2Te_5$ and $Sb_2Te_3$ films were deposited on $SiO_2/Si$ substrates by RF sputtering system. In order to characterize the crystal structure and morphology of these films. x-ray diffraction (XRD). atomic force microscopy (AFM), differential scanning calorimetry (DSC) and 4-point measurement analysis were performed. XRD and DSC analysis result of GST thin films indicated that the crystallization of $Se_2Sb_2Te_5$ films start at about $180^{\circ}C$ and $Sb_2Te_3$ films Start at about $125^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.08a
• /
• pp.282-282
• /
• 2011

Low power consuming operation of phase-change random access memory (PRAM) can be achieved by confining the switching volume of phase change media into nanometer scale. Ge2Sb2Te5 (GST) is one of the best materials for the phase change random access memory (PRAM) because the GST has two stable states, namely, high and low resistance values, which correspond to the amorphous and crystalline phases of GST, respectively. However, achieving the fast operation speed at lower current requires an alternative chalcogenide material to replace the GST and shrinking the dimension of programmable volume. In this paper, we have fabricated nanoscale contact area on Ge2Sb2Te5 thin films with trimming process. The GST material was fabricated by melt quenching method and the GST thin films were deposited with thickness of 100 nm by the electron beam evaporation system. As a result, the reset current can be safely scaled down by reducing the device contact area and we could confirmed the phase-change characteristics by applying voltage pulses.

• Journal of Astronomy and Space Sciences
• /
• v.29 no.3
• /
• pp.315-320
• /
• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

• Asian-Australasian Journal of Animal Sciences
• /
• v.25 no.4
• /
• pp.541-551
• /
• 2012

The effects of dietary additives and holding time on resistance and resilience of broiler chickens to Clostridium perfringens challenge were investigated by offering four dietary treatments. These were a negative control (basal), a positive control (Zn-bacitracin) and two dietary additives, mannanoligosaccharides (MOS), and acidifier. Two holding times included (a) immediate access to feed and water post hatch (FED) and (b) access to both feed and water 48 h post hatch (HELD). Chicks fed Zn-bacitracin had no intestinal lesions attributed to necrotic enteritis (NE), whereas chicks fed both MOS or acidifier showed signs of NE related lesions. All dietary treatments were effective in reducing the numbers of C. perfringens in the ileum post challenge. The FED chicks had heavier body weight and numerically lower mortality. The FED chicks also showed stronger immune responses to NE challenge, showing enhanced (p<0.05) proliferation of T-cells. Early feeding of the MOS supplemented diet increased (p<0.05) IL-6 production. The relative bursa weight of the FED chicks was heavier at d 21 (p<0.05). All the additives increased the relative spleen weight of the HELD chicks at d 14 (p<0.05). The FED chicks had increased villus height and reduced crypt depth, and hence an increased villus/crypt ratio, especially in the jejunum at d 14 (p<0.05). The same was true for the HELD chicks given dietary additives (p<0.05). It may be concluded that the chicks with early access to dietary additives showed enhanced immune response and gut development, under C. perfringens challenge. The findings of this study shed light on managerial and nutritional strategies that could be used to prevent NE in the broiler industry without the use of in-feed antibiotics.

• Journal of KIISE:Computer Systems and Theory
• /
• v.37 no.5
• /
• pp.285-291
• /
• 2010

Flash memory has many good features such as small size, shock-resistance, and low power consumption, but the cost of flash memory is still high to substitute for hard disk entirely. Recently, some mobile devices, such as laptops, attempt to use both flash memory and hard disk together for taking advantages of merits of them. However, existing OSs (Operating Systems) are not optimized to use the heterogeneous storage media. This paper presents a new buffer cache management scheme. First, we allocate buffer cache space according to access patterns of block references and the characteristics of storage media. Second, we prefetch data blocks selectively according to the location of them and access patterns of them. Third, we moves destaged data from buffer cache to hard disk or flash memory considering the access patterns of block references. Trace-driven simulation shows that the proposed schemes enhance the buffer cache hit ratio by up to 29.9% and reduce the total I/O elapsed time by up to 49.5%.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.419-422
• /
• 2004

A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.