• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1323-1333
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• 1997

In this paper, we propose an efficient architecture for a high-speed cell concentrator/distributor(HCCD) in an ATM(Asynchronous Transfer Mode) switch and by analyzeing the simulation results evaluate the performance of the proposed architecuture. The proposed HCCD distributes cells from a switch link to local processors, or concentrates cells from local processor s to a switch link. This design is to guarntee a high throughput for the IPC (inter-processor communication) link in a distributed ATM switching system. The HCCD is designed in a moudlar architecture to provide the extensibility and the flexibility. The main characteristics of the HCCD are 1) Adaption of a local CPU in HCCD for improving flexibility of the system, 2) A cell-baced statistical multiplexing function for efficient multiplexing, 3) A cell distribution function based on VPI(Virtual Path Identifier), 4) A bypassing capability for IPC between processor attached to the same HCCD, 5) A multicasting capability for point-to-multipoint communication, 6) A VPI table updating function for the efficient management of links, 7) A self-testing function for detecting system fault.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1597-1602
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• 1999

An analog / digital mixed mode frequency multiplication and distribution ASIC for switch link or network synchronization of ATM switching system for B-ISDN has designed. This ASIC generates 234-7 MHz system clock and 77.76 MHz, 19.44 MHz user clocks using 46.94 MHz external clock. It also includes digital circuits for checking and selecting between the two external clocks. For effective ASIC design, full custom technique is used in analog PLL circuit and standard cell based technique is used in digital circuit. Resistors and capacitors are specially designed so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.285-288
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• 1998

In this paper, we present mSROS(Micro-Scalable Realtime Operating System) to be applied commonly to the device controller systems in the HANbit ACE256 system. The device controller systems in HANbit ACE256 system are organized as many kinds of device controller. Applying modified PPOS(Peripheral Processor Operating System)which is an operating system for devices of the TDX-10 switching system to the firmwares for them, the inefficiency in development and maintenance exists inherently. To remove the inefficiency nd to improve the performqance of firmwares, we build a common operating system platform that including multi-tasking microkernel so that the firmwares among devices can acquire convenient development and cheap cost of maintencance. Especially, building a virtual machine as a development methodology, it is possible to remove dependency from the kernel so that any kinds of commercial real-time kernels can be used in mSROS as a basic kernel. The virtual machine in mSROS is compatible with the API of SROS(Scalable Realtime Operating System), PPOS, and CROS(Concurrent Realtime Operating System).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.241-249
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• 2005

ATM based MPLS(Multiprotocol Label Switching) is discussed for its provisioning QOS commitment capabilities, Traffic engineering and smooth migration for BcN in Korea. At this time, due to the comprehensive nature of ATM protocol, ATM has been adapted as the backbone system for carrying Internet traffic[1,2,3,4]. This paper presents preventive congestion control mechanisms for detecting HTR(Hard-To-Reach) LSP(Label Switched Path) in ATM based MPLS systems. In particular, we have introduced a HTR LSP detection method using network signaling information in an ATM layer. MPLS related studies can cover LSP failures in a physical layer fault, it can not impact network congestion status. Here we will present the research results for introducing HTR LSP detection methods and control mechanisms and this mechanism can be implementing as SOC for high speed processing a packet header. We concluded that it showed faster congestion avoidance abilities with a more reduced system load and maximized the efficiency of network resources by restricting ineffective machine attempts.

• Journal of KIISE:Information Networking
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• v.29 no.1
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• pp.40-47
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• 2002

This paper analyzes the performance of an optical line termination system in ATM based Passive Optical Network(PON) using the operational analysis. We analyze it using system parameters such as utilization, throughput and routing frequency based on the buffer structure in each block of ATM-PON. Furthermore, we derive the mean response time and the visit ratio of each block, and then search the bottleneck block that hinders the system performance. We found that the 622Mbps 16x16 switching block is the bottleneck block for ATM-PON. In this bottleneck block, the loss probability increases rapidly when the cell arrival rate increases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1899-1906
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• 1998

In ATM switching system link bandwidth is one of the improtant resources. Thus ATM switching system must allocate the bandwidth to the users efficiently and guarantee the QoS. Especially to guarantee the QoS of the VBR traffic source such as video, users must declare the traffic characteristics and QoS expectations using UPC parameters. The CAC can use two multiplexig models in variation to link capacity and connection number. One is loseless multiplexing model; the second is a statistical multiplexing model. The loseless multiplexing model performs best when the number of mutiplexed sources is small, but as the number of multiplexed sources is increase the CAC must use the statistical multiplexing model. In this paper, the statistical multiplexing models are studied, which are suitable for high capacity ATM link on VBR traffic sources. The satistical multiplexing model and the loseless multiplexing model are combined. In statistical model we map the UPC parameters provided by new VBR connection to appropriate source traffic model. In the high capacity ATM link, as the connection number increases, the statical multiplexing gain increases.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.25-35
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• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• Journal of KIISE:Information Networking
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• v.30 no.2
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• pp.270-281
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• 2003

ETF made the RFCs of MPLS technologies for providing the QoS of ATM or Frame Relay and the flexibility&scalability of IP on the Internet services. IETF has been expanding MPLS technologies as a common control component for supporting the various switching technologies called GMPLS. Also, IETF has standardized the signaling protocols based on such technologies, such as LDP, CR-LDP and RSVP-TE. ETRI developed the MPLS system based on ATM switch in order to provide more reliable services, differentiated services and value-added services like the VPN and traffic engineering service on the Korea Public Sector network. We are planning on deploying model services and commercial services on that network. This paper explains the basic functions of LDP, design and development of LDP on our system, and compares with LDP development and operation on other MPLS systems made by Cisco, Juniper, Nortel and Riverstone. In conclusion, this paper deduces the future services and applications by LDP through these explanation and comparison.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.1-9
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• 1998

ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.