• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1184-1195
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• 1998

In this paper, we compare vaious input-buffered ATM switch architectures in structures on input buffer and switching fabric, the resons for performance improvement and degradation, arbitration scheme and maximum throughput, and present comparative merits and demerits of each architecture under random and bursty traffic. We also analyze the prformance of combined architectures of windowing scheme, destination-queueing based input-port expansion schemeand output-port expansion scheme, and show that it is possible to achieve 100% throughput with combined scheme of destination-queueing based input-port expansion scheme and output-port expansio scheme when the number of output group is 2 and output port expansion ratio is 2.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.569-580
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• 2003

One of the important advantages of multichannel switches is the incorporation of inherent fault tolerance into the switching fabric. For example, if a link which belongs to the multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if faults occur in the switching elements, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithms in multichannel crossbar ATM switches with a view to early fault recovery, The optimal algorithm gives the best performance in terms of time to localization but is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally mote efficient than the optimal algorithm. We evaluate its performance through simulation. The simulation results show that performance of the on line algorithm is only slightly sub-optimal for both random and bursty traffic. Finally a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm.

• Journal of Internet Computing and Services
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• v.3 no.5
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• pp.9-17
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• 2002

CSIX-L1 is the Common Switch Interface that defines a physical interface for transferring information between a traffic manager (Network Processor) and a switching fabric in ATM, IP, MPLS, Ethernet and data communication areas. In Tx, data to be transmitted is generated in Cframe which is the base information unit and in Rx, original data is extracted from the received Cframe. CSIX-L1 suppots the 32, 64, 96, and 123-bit interface and generates a variable length CFrame and Idle Cframe. Also CSIX-L1 appends Padding byte and supports 16-bit Vertical parity, CSIX-L1 is designed using Xilinx 4,1i. After functional and timing simulations are completed. CSIX-L1 module is downloaded in Xilinx FPGA XCV1000EHQ240C and verified. The synthesized CSIX module operates at 27MHz.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1941-1948
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• 2000

Multistage interconnection networks (MINs) have been recognized as an efficient interconnection network for high-performance computer systems and also have been recently identified to be effective for a switching fabric of new communication structures - gigabit ethernet switch, terabit router, and ATM (asynchronous transfer mode). While lots of models analyzing the performance of MINs have been proposed, they are either inaccurate or, even if accurate, very complex for the analysis. In this paper, we propose an extremely simple mode for evaluating the multibuffered MIN with small clock cycles based on the approximation approach. Comprehensive computer simulation shows that the proposed model is very accurate in terms of the throughput and mean delay. Furthermore, it significantly reduces the computing overhead due to its simplicity.