• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.57-63
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• 2003

In this paper, we propose the hardware architecture of a scale converter which is to convert a variety range of scale into a target scale and a time sequential color control driver for LOCS (Liquid Crystal On Silicon) micro display devices which are considered advanced micro display technology in the next generation. The driver has been implemented and tested with ASIC chips.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.19-20
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• 2009

H.264 부호기의 on-chip 상의 구현방법으로는 성능에 중점을 둔 ASIC (application specific integrated circuit) 기반의 접근 방식과 ASIC 보다 성능은 떨어지나 일반성과 유연성에 중점을 둔 ASIP (application specific instruction set architecture) 기반의 설계 방식이 연구되어 왔다. 우리는 영상 압축 응용 범위 내에서는 일반성 및 유연성을 잃지 않으면서도 기존에 문제시 되던 ASIP의 성능은 대폭 개선할 수 있는 ISA와 micro architecture를 제안하고 구현한 바 있다. 본 논문의 핵심적인 기여는 이 ASIP의 추가적인 성능 개선이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.63-70
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• 2011

In this paper, we are implemented the kasumi cipher algorithm by hardware. In this work, kasumi was designed technology-independently for application such as ASIC or core-based design. The hardware is implemented to be able to calculate both confidentiality and integrity algorithm, and a pipelined KASUMI hardware is used for a core operator to achieve high operation frequency. The proposed block cipher was mapped into EPXA10F1020C1 from Altera and used 22% of Logic Element (LE) and 10% of memory element. The result from implementing in hardware (FPGA) could operate stably in 36.35MHz. Accordingly, the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.50-58
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• 2013

In this paper, we present the implementation result of an UWB terminal for mobile tactical networks. Considering the major characteristics of the terminals of tactical networks, i) targeting voice service, ii) pedestrian users, and iii) demanding high network fidelity, we designed all protocol layers from physical layer to applications layer. The designed terminal is implemented in forms of software and hardware with RF ASIC, FPGA, DSP, and GPP. The functionality of the implemented terminal is validated by successfully performing 1 to 1 and multi-hop voice communication test.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1993.10a
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• pp.441-445
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• 1993

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.403-406
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• 2001

본 논문에서는 차세대 표준 알고리즘(AES: Advanced Encryption Standard)인 Rijndael 알고리즘의 고속화를 FPGA로 구현하였다. Rijndael 알고리즘은 미국 상무부 기술 표준국(NIST)에 의해 2000년 10월에 차세대 표준으로 선정된 블록 암호 알고리즘이다. FPGA(Field Programmable Gate Array)는 아키텍쳐의 유연성이 가장 큰 장점이며, 근래에는 성능면에서도 ASIC에 비견될 정도로 향상되었다. 본 논문에서는 128비트 키 길이와 블록 길이를 가지는 암호화(Encryption)블럭을 Xilinx VirtexE XCV812E-8-BG560 FPGA에 구현하였으며 약 15Gbits/sec의 성능(throughput)을 가진다. 이는 현재까지 발표된 FPGA Rijndael 알고리즘의 구현 사례 중 가장 빠른 방법 중의 하나이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.859-870
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• 2000

In this paper, an efficient H/W implementation technique for guard interval in OFDM(Orthogonal Frequency Division Multiplexing) systems is proposed and applied to ASIC chip design of an OFDM-based 25 Mbps wireless ATM modem. In OFDM systems, a cyclic prefix, longer than the largest multipath delay spread, is usually inserted to maintain the orthogonality of subchannels, by making the linear convolution of the channel ok like circular convolution inherent to the discreate Fourier domain, as well as to prevent the ISI(Intersymbol Interference) within the OFDM block. However, the OFDM system using the cyclic prefix requires an additional H/W in transmitter in order to store the original samples and to append the cyclic prefix to the beginning of each block. In this paper, a new approach using a cyclic prefix, even with a significantly lower H/W complexity. Finally, the performance of the proposed approach is demonstrated by applying it to ASIC chip design of an OFDM-based 25 Mbps wireless ATM modem.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.6
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• pp.48-55
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• 2001

This paper presents a 1.8 GHz CMOS frequency synthesizer with high-speed on-chip pseudo 2-stage ring VCO. We introduce and analysis the conditions in which the ring VCO can oscillate. For high speed operation, we propose the pseudo 2-stage ring VCO that eliminates dummy loads. It can operate up to 1.87 GHz with 0.6 m CMOS process, which shows 21.3% improvement aginst the conventional 4-stage ring VCO in the aspect of the speed. When the frequency synthsizer with the psedo 2-stage ring VCO is locked at 1.85GHz, the jitter measured to 24 psec. The proposed VCO and the frequency synthesizer are directly applicable to high speed clocky synhtesizers.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.6
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• pp.481-488
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• 2021

The satellite telecommand processing system is the only way to provide telecommands for status monitoring, control, and mission execution. Domestic satellites can be divided into science, technology, and multi-purpose satellites, and geostationary satellites. These Satellites uses CCSDS standard protocol to communicate with ground stations. However, existing domestic satellites use only software to decode telecommands which increases cost of software development and verification of the developed software. Performance of software only approach is relatively low compared to hardware. In this paper, we present ASIC processing system specifically designed to decode telecommands. The system consists of a telecommand RAM, a protocol RAM/ROM, an ASIC, an interface unit of FPGA, and a relay block. The system handles general commands and pulse commands that are used in satellites. We established a ground station equipment and test environment to verify the system functionality, The result shows that our system reduces the development cost by 1/5 and improves the performance by 10⁵ times compared to the previous systems that decode telecommands only by software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2141-2152
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• 1998

In this paper, we design and implement an indoor wireless modem using small signal of ISM band regulation, which can tranceive reliable data streams. We use direct sequence spead spectrum (DS-SS) signaling with synchronous BPSK and QPSK modulation, convolutional coding with viterbi decoding. The radio frequency module uses frequency devision duplexing in 900 MHz band, and the digital module is implemented with FPGAs for the purpose fo ASIC design. The perfomrance of our own acquistion and tracking circuit consisting digital matched filter and decision logic is proved by experiments, and the possibility of file transfer at indoor environment with the entrie system that the modem is connected the PC through RS-232C port is verified.