• Title/Summary/Keyword: AS/RS Design

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Design and Performance Evaluation of RS Codec for DTMF Modulation in Mobile Radio Channels (이동무선 채널에서 DTMF 변조 방식에 대한 RS 복부호기의 설계 및 성능평가)

  • 송문규;이상설;김우현
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.1
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    • pp.133-140
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    • 1998
  • In this paper, RS coded DTMF modulation for reliable data transmission over mobile fading channels is considered. The circuits of (15,9) RS codec are proposed and synthesized, and the performances are evaluated over fading channels. The codec circuits take about 14000 gates standardized by 2-input NAMD gate. The (15,9) RS coded DTMF signalling provides theoretical coding gain more than 20 dB over fading channels for BER 10.6, the criterion for data transmissions in mobile communications such as IMT-2000. Thus, It is very effective to apply RS codec to DTMF signalling for data transmission in mobile communications over fading channels.

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Design of an Adaptive Reed-Solomon Decoder with Varying Block Length (가변 블록길이를 갖는 적응형 리드솔로몬 복호기의 설계)

  • Song, Moon-Kyou;Kong, Min-Han
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.4C
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    • pp.365-373
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    • 2003
  • In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

A Computer Simulation Study of an Automated Storage and Retrieval System (자동창고 시스템의 컴퓨터 시뮬레이션 연구)

  • Kim, Kwang-Soo;Choi, Young-Hwan
    • IE interfaces
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    • v.3 no.2
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    • pp.39-51
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    • 1990
  • One of the most important and powerful tools available for design and/or study of the operation of complex systems and processes is simulation. Since automated material handling systems like AS/RS are often quite complex, a network-based simulation model is developed to analyze an automobile part supplier's automated storage and retrieval system(AS/RS). The network simulation model is implemented in the SLAM Ⅱ on a VAX 8800 computer. Performance of the AS/RS was tested for 3 dispatching rules, 3 work load levels, 2 storage policies, 3 levels of stacker crane break-down, and 2 conveyor system layouts. Results indicate that the AS/RS performance is primarily affected by the dispatching rule and work load level.

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Design of Degree-Computationless Modified Euclidean Algorithm using Polynomial Expression (다항식 표현을 이용한 DCME 알고리즘 설계)

  • Kang, Sung-Jin;Kim, Nam-Yong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.10A
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    • pp.809-815
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    • 2011
  • In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

Single Relay Selection for Bidirectional Cooperative Networks with Physical-Layer Network Coding

  • Liu, Yingting;Zhang, Hailin;Hui, Leifang;Liu, Quanyang;Lu, Xiaofeng
    • ETRI Journal
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    • v.34 no.1
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    • pp.102-105
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    • 2012
  • To serve the growing demand of the bidirectional information exchange, we propose a single relay selection (RS) scheme for physical-layer network coding (PNC) in a bidirectional cooperative network consisting of two sources and multiple relays. This RS scheme selects a single best relay by maximizing the bottleneck of the capacity region of both information flows in the bidirectional network. We show that the proposed RS rule minimizes the outage probability and that it can be used as a performance benchmark for any RS rules with PNC. We derive a closed-form exact expression of the outage probability for the proposed RS rule and show that it achieves full diversity gain. Finally, numerical results demonstrate the validity of our analysis.

PLC and Arduino Interaction Based on Modbus Protocol

  • Jeong, Yunju;Ansari, Md Israfil;Shin, WooHyeon;Kang, Bonggu;Lim, JinSeop;Moon, HyeonSik;Shim, Jaechang
    • Journal of Korea Multimedia Society
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    • v.20 no.3
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    • pp.511-519
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    • 2017
  • This Paper introduces the design and communication method between PLC (Programmable Logic Controller) and Arduino based on MODBUS Protocol. MODBUS connection can be established in a new or existing system very easily, therefore we used this protocol in our proposed system. In the field of automatic devices, multi-function serial port such as RS232, RS422, RS485, and so on creates a great convenience to the developer. This proposed system used RS485 as a key mediator for data exchanging on a connected network. We also believe that it will reduce the development cost in various automated industry because this system can be reused or can be implemented any such PLC installed machines. RS485 is used as a communication interface between PLC (as a slave) and Arduino (as a master), through which a reliable network is created for safe and fast communication. Furthermore, RS485 allows multiple devices(up to 32) to communicate at half duplex on a single pair of wires and provides a long connectivity area (up to 1200 meters) as compare to other device, which makes it a user-friendly for various devices in the automated industry. Moreover, Arduino can play as a mediator by connecting third party device and setup a communication network with PLC.

The invariant design of planar magnetron sputtering TFT-LCD

  • Yoo, W.J.;Demaray, E.;Hosokawa;Pethe, R.
    • Journal of Korean Vacuum Science & Technology
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    • v.3 no.2
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    • pp.101-106
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    • 1999
  • The main consideration factor to design a magnetron of the sputtering system for TFT-LCD metallization is high sheet resistance (Rs) uniformity which is provided by the high target erosion and high current efficiency. The present study has developed a rectangular magnetron for TFT-LCD to bve considered full target erosion and high film uniformity. After an aluminum-2 at.% and alloy target was installed in a magnetron source and the film was deposited on the glass of 600${\times}$720 mm, the Rs uniformity of the deposited film was measured as functions of the magnet tilt and magnet scanning configuration. And the target erosion profile was observed with the target voltage. When sputtered at 4mtorr and 10kW, the magnet tilt for the high Rs uniformity of 8.38% was 7mm. The plasma voltage at the dwell home and end for full-face target erosion, when scanned the magnetron was 120% compared to the mean voltage of the other area.

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EFFECT OF ADDITION OF INTACT OR ALKALIZED LUCERNE JUICE AT ENSILING ON THE NUTRITIVE VALUE OF RICE STRAW SILAGE

  • Nishino, N.;Ohshima, M.;Yokota, H.
    • Asian-Australasian Journal of Animal Sciences
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    • v.5 no.3
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    • pp.487-494
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    • 1992
  • This experiment was conducted to study the effect of addition of Lucerne juice (LJ) obtained by mechanical extraction of freshly harvested crop on the nutritive value of rice straw silage. Rice straw (RS) was ensiled with intact, NaOH or $NH_3$ treated LJ at 3:7 ratio on fresh weight basis (LJ RS, LJ NaOH RS and LJ $NH_3$ RS, respectively). Each alkali was mixed with fresh juice at a level of 4% of rice straw dry matter just before ensiling. Rice straw ensiled with water was prepared as the control (W RS). In the digestion trial, goats were allocated in a $4{\times}4$ Latin-square design and fed the diet containing three parts of RS silage and one part of wheat bran (DM basis). For the goats receiving the control silage, urea was supplemented at feeding time so as to adjust the nitrogen intake except for goats on LJ $NH_3$ RS silage. Crude protein content of RS silage was increased from 5.2 to 9.1% (DM basis) by the addition of intact LJ and to about 24% by $NH_3$ treated LJ. The control W RS silage contained only trace amount of lactic acid and was dominated by acetic and butyric acid. The addition of intact LJ reduced butyric acid content and $NH_3-N/TN$ of the silage whereas the addition of alkalized LJ increased those values and shifted to a butyrate type fermentation. Nutrient digestibilities and nitrogen balance of goats were almost the same when they were fed W RS and LJ RS silage indicating the addition of intact LJ did not improve the nutritive value. The addition of alkalized LJ significantly increased the fiber digestibilities of RS silage and $NH_3$ treatment was more effective than NaOH treatment. Postprandial ruminal $NH_3-N$ and blood urea nitrogen (BUN) concentrations were decreased by feeding LJ NaOH RS silage suggesting ruminal protein synthesis was enhanced along with the increase of energy supply for supply for rumen microbes by the alkali treatment. The advantageous fiber digestibilities of LJ $NH_3$ RS silage compared with those of LJ NaOH RS silage might be attributable to a sufficient nitrogen supply for microbial fiber digestion in the rumen.

Vibration Properties of Concrete Overlays using RS-LMC (초속경 LMC를 이용한 콘크리트 포장의 진동특성)

  • Kim, Min-June;Shin, Geun-Ock;Joo, Nak-Chin;Lee, Gwang-Jo;Jeong, Je-Pyong
    • Journal of the Korea Concrete Institute
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    • v.28 no.5
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    • pp.571-579
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    • 2016
  • RS-LMC (Rapid Setting Latex Modified Concrete) has been widely used as repair material for bridge deck overlay or rehabilitation, because the overlaid pavement could be opened to the traffic after 3 hours of curing. Although the field performance of RS-LMC generally indicates that it has an excellent bonding to the substrate and shows a long term performance, the crack by vibration of vehicles have been happened on the overlay of bridges in technical reports. In this study, experimental research was carried out to evaluate the vibration properties of RS-LMC overlays by using P.S.T (Pavement Shaking Table). Total 12 specimens were tested and the variables are Latex-cement ratio (L/C) and amplitude of vibration. The result shows that the number of cracks and the total length of cracks are reduced as the increase of Latex-cement ratio (L/C) until 15%. And the crack occurs at a very small strain than the proposed values by Walter, D, G and design codes.

Design and synthesis of reed-solomon encoder and decoder using modified euclid's algorithm (수정된 유클리드 알고리듬을 적용한 리드솔로몬 부호기 및 복호기의 설계 및 합성)

  • 이상설;송문규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.6
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    • pp.1575-1582
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    • 1998
  • Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

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