• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.166-168
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• 2007

This paper is dealing with how to control of a client robot's movement for instructions from a server PC and a wireless andremote control Robot that sends the server information of images for monitoring. To implement this. 802.11x WLAN with TCP/IP socket programming is used to get the driving instructions from the server PC and control movements of the robot such as a forward, backward and directions. As well as this, ARM9 cored PAX255 embedded processor and Linux OS is used for the function transmitting BMP format of 320 ${\times}$ 240 pixel for stopped image data.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.10-11
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• 2016

실시간 시스템이란 요청된 작업의 논리적 정확성과 시간적 제약을 만족하게 하는 시스템으로 요청된 작업을 예측 가능한 시간 내에 완료하는 시스템을 말한다. 범용 운영체제인 Linux는 실시간성을 지원하지 않기 때문에 ARM 프로세서(Processor) 기반의 Linux 환경에서도 실시간성을 제공하기 위해 본 연구를 진행한다. 본 연구는 Exynos 5422 ARM 프로세서에서 제공하는 타이머를 활용하여 실시간성을 확보하여 Linux 환경에 대한 실시간성 지원 제약을 해결할 수 있다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.10
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• pp.446-451
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• 2006

In this paper, we propose an implementation of JPEG2000 codec on the ARM9 Processor which includes independent memory management facility. The codec and memory management facility together can control the encoding and the decoding process effectively within available memory area. Embedded appliances like cellular phones have very limited internal memory which can't be expanded easily. However, they should provide various applications and services using restricted memory resources. The proposed codec with memory management can provide image quality that is identical to the original image on embedded platform. The implemented codec has no memory conflict with other applications. It shows that the proposed codec can manage memory resources efficiently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.188-194
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• 2007

In order to become ubiquitous world, the compatibility of wireless machines has become the significant characteristic of a communication terminal. Thus, SDR is the most necessary technology and standard. However, among the environment which has different communication protocol, it's difficult to make a terminal with only hardware using ASIC or SoC. This paper suggests the processor that can accelerate several communication protocol. It can be connected with main-processor, and it is specialized PHY layer of network The C-program that is modeled with the wireless protocol IEEE802.11a and IEEE802.11b which are based on widely used modulation way; OFDM and CDM is compiled with ARM cross compiler and done simulation and profiling with Simplescalar-Arm version. The result of profiling, most operations were Viterbi operations and complex floating point operations. According to this result we suggested a co-processor which can accelerate Viterbi operations and complex floating point operations and added instructions. These instructions are simulated with Simplescalar-Arm version. The result of this simulation, comparing with computing only one ARM core, the operations of Viterbi improved as fast as 4.5 times. And the operations of complex floating point improved as fast as twice. The operations of IEEE802.11a are 3 times faster, and the operations of IEEE802.11b are 1.5 times faster.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.363-372
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• 2015

Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.99-105
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• 2021

Today, a superscalar processor is the basic unit or an essential component of a multi-core processor, SoCs, and GPUs. Hence, a high-performance out-of-order superscalar processor must be adopted for these systems to maximize its performance. The superscalar processor fetches, issues, executes, and writes back multiple instructions per cycle by utilizing reorder buffers and reservation stations to dynamically schedule instructions in a pipelined scheme. In this paper, a fully pipelined out-of-order superscalar processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, the program composed of ARM instructions is successfully performed.

• Proceedings of the KIEE Conference
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• 2008.04a
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• pp.59-60
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• 2008

In this paper, we investigate the ability of the ARM processor to implement an industrial controller with or without embedded operating system. Discrete-time PID controllers are implemented and tested under various settings e.g. cache on/off, different clock frequencies using S3C2410X chip. A method of real-time application of discrete-time PID controller in WinCE environment is proposed. Based on the test result, we provide the maximum sampling frequencies of PID controller using ARM processor.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.200-203
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• 2000

In this paper, we describes the design of a CPU compatible with ARM9 processor. The CPU is fully synthesizable and described in Verilog-XL. Starting from the synthesizable ARM7 compatible CPU we developed earlier, we modified its pipeline to five stages. For this we first partition the behaviors of each instruction into five stage pipeline operations. Then we designed the controller and the datapath considering the forwarding or interlock schemes. Finally the compatibility of the designed CPU is verified by comparing the results of every instruction executed in test programs with those of the reference simulator developed for the ARM7 compatible CPU.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.466-468
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• 2000

ARM 프로세서는 CISC 보다는 간단하게 디자인된 RISC로서 내장 응용프로그램에 적합하기 때문에 앞으로 모든 디지털 기기에 ARM 코어를 기반으로 한 핵심 칩들이 생산된다. 그러나 명령어가 CISC보다는 적기 때문에 주어진 작업에 대해 완전한 처리를 위해서는 보다 많은 명령어들을 필요로 한다. 이러한 ARM 프로세서에서 데이터를 전송할 때 사용하는 메모리 영역과 레지스터들을 프로그램과 함께 분석하였다.