• Title/Summary/Keyword: ARM architecture

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Prediction of Hydrodynamic Coefficients for Underwater Vehicle Using Rotating Arm Test (강제선회시험을 이용한 수중운동체의 유체력 미계수 추정)

  • Jeong, Jae-Hun;Han, Ji-Hun;Ok, Jihun;Kim, Hyeong-Dong;Kim, Dong-Hun;Shin, Yong-Ku;Lee, Seung-Keon
    • Journal of Ocean Engineering and Technology
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    • v.30 no.1
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    • pp.25-31
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    • 2016
  • In this study, hydrodynamic coefficients were obtained from a Rotating Arm (RA) test, which is one of the captive model tests used to provide accurate coefficients in the control motion equation of an underwater vehicle. The RA test was carried out at the RA facility of ADD (Agency for Defense Development), and the forces and moments acting on the underwater vehicle were measured using a six-axis waterproof gage. A multiple regression analysis was used in the analysis of the measured data. The experimental results were also verified by comparison with the theoretical values of the previous linear coefficients. In addition, the stability indices in the horizontal plane were calculated using the linear and nonlinear coefficients, and the dynamic stability of the underwater vehicle was estimated to have a good dynamic performance with a depth ratio of 6.0.

A Speed-up Method of HOG Pedestrian Detector in Advanced SIMD Architecture (Advanced SIMD 아키텍처에서의 HOG 보행자 검출기 고속화 방법)

  • Kwon, Ki-Pyo;Lee, Jae-Heung
    • Journal of IKEEE
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    • v.18 no.1
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    • pp.106-113
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    • 2014
  • A pedestrian detector can be applied for various purposes such as monitoring or counting the number of people in some place, or detecting the people plunging in the driveway. There was a lot of related research. But, the detection speed is slow in embedded system because of the limited computing power. An algorithm for fast pedestrian detector using HOG in ARM SIMD architecture is presented in this paper. There is a way to quickly remove the background of image and to improve the detection speed using NEON parallel technique. When we tested with INRIA Person Dataset, the proposed pedestrian detector improves the speed by 3.01 times than previous one.

Synthesis and Characterization of Linear and Branched Copolymers of Poly(ethylene glycol) and $Poly({\varepsilon}-caprolactone)$ (선형 및 분지 구조의 폴리(에틸렌 글리콜)/폴리카프로락톤 공중합체의 합성 및 특성 검토)

  • Hyun Hoon;Kim Moon-Suk;Khang Gil-Son;Rhee John-M.;Lee Hai-Bang
    • Polymer(Korea)
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    • v.30 no.2
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    • pp.146-151
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    • 2006
  • Linear and branched copolymers consisting of poly(ethylene glycol) (PEG) and $Poly({\varepsilon}-caprolactone)$ (PCL) were prepared to compare the characterization of star-shaped copolymers with various molecular architecture. Linear and branched PEG-PCL (1-arm, 2-arm, 4-arm, and 8-arm) copolymers were synthesized by the ring-opening polymerization of ${\varepsilon}-caprolactone$ in the presence of HCl $Et_2O$ as a monomer activator at room temperature. The synthesized copolymers were characterized with $^1H-NMR$, GPC, DSC, and XRD. As a result of the DSC and XRD, each copolymers showed different thermal properties and crystallinity according to the number of ms. The micellar characterization of linear and branched copolymers in an aqueous phase was carried out by using NMR, dynamic light scattering, AM, and fluorescence techniques. The critical micelle concentration (CMC) and diameters of micelles depended on the number of arms. Most micelles exhibited a spherical shape in AFM. In this study, we characterized star-shaped PEG-PCL copolymers and investigated their molecular architecture effect on the various properties. Furthermore, we confirmed that the micelles termed with linear and branched PEG-PCL copolymers have possibility as a potential hydrophobic drug delivery vehicle.

A Hardware-Software Interface Design in the Codesign Environment (혼합 설계 환경에서의 하드웨어-소프트웨어 인터페이스 설계)

  • 장준영;배영환
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.120-123
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    • 2000
  • In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

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Attributed AND-OR Graph for Synthesis of Superscalar Processor Simulator (슈퍼스칼라 프로세서 시뮬레이터의 생성을 위한 Attributed AND-OR 그래프)

  • Jun Kyoung Kim;Tag Gon Kim
    • Proceedings of the Korea Society for Simulation Conference
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    • 2003.06a
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    • pp.73-78
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    • 2003
  • This paper proposes the simulator synthesis scheme which is based on the exploration of the total design space in attributed AND-OR graph. Attributed AND-OR graph is a systematic design space representation formalism which enables to represent all the design space by decomposition rule and specialization rule. In addition, attributes attached to the design entity provides flexible modeling. Based on this design space representation scheme, a pruning algorithm which can transform the total design space into sub-design space that satisfies the user requirements is given. We have shown the effectiveness of our framework by (ⅰ) constructing the design space of superscalar processor in attributed AND-OR graph (ⅱ) pruning it to obtain the ARM9 processor architecture. (ⅲ) modeling the components of the architecture and (ⅳ) simulating the ARM9 model.

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Porting Window CE Operating System to Arm based board device

  • An, Byung-Chan;Ham, Woon-Chul
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2159-2163
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    • 2003
  • Hand carried computing machinery and tools have been developed into an embedded system which the small footprint operating system is contained internally. Windows CE which is one of imbedded operating system is a lightweight, multithreaded operating system with an optional graphical user interface. Its strength lies in its small size, its Win32 subset API, and its multiplatform support. Therefore we choose to port this OS on Arm based board that is provided high performance, low cost, and low power consumption. In this paper, we describe the architecture of ARM based board, the feature of Windows CE, techniques and steps involved in this porting process.

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Design of an ARM9 Compatible 32bit RISC Microprocessor (ARM9 호환 32bit RISC Microprocessor의 설계)

  • Hwang, Bo-Sik;Nam, Hyoung-Gin
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.885-888
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    • 2005
  • In this study, we designed an ARM9 compatible RISC microprocessor using VHDL. The microprocessor was designed to support Harvard architecture with separate instruction cache and data cache. The state machine was optimized for multi-cycle instructions. In addition, a data forwarding mechanism was adopted to reduce the stall cycles due to data hazards. Assembly programs were up-loaded into a ROM block for system-level simulation. Proper operation of the designed microprocessor was confirmed by investigating the contents of the internal registers as well as the RAM block. Futhermore, the simulation results clearly indicated that the operation speed of the processor designed in this study is enhanced by reducing the execution cycles required for multiplication related instructions.

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Design of Embedded Platform based on Android (안드로이드 기반 임베디드 플랫폼 설계)

  • Yoon, Chan-Ho;Kim, Gwang-Jun;Jang, Chang-Soo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.10
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    • pp.1545-1552
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    • 2013
  • This paper presents an implementation of embedded platform based ARM A8-cortex processor for android supporting. The development board for S5PV210 is a platform that is suitable for code development of SAMSUNG's S5PV210 32bit RICS micro controller(ARMv7) architecture for hand-held device and general applications. Embedded platform development board offers various function and high efficiencies. In addition to the high performance, the embedded platform offers low current consumption, ensuring low costs and power.

Fast pedestrian detector using HOG in ARM architecture (HOG를 이용한 ARM 아키텍처에서의 고속 보행자 검출기)

  • Kwon, Ki-Pyo;Lee, Jae-Heung;Kang, Byung-Ik
    • Proceedings of the Korea Information Processing Society Conference
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    • 2013.11a
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    • pp.161-164
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    • 2013
  • 보행자 검출기는 보안이 필요한 곳에서 모니터링을 하거나 특정 장소를 드나드는 사람의 수를 셀 때, 운전 중 차도에 뛰어드는 사람을 감지할 때 등 상황에 따라 여러 목적으로 응용될 수 있다. 이에 따른 연구는 많이 진행되어 왔지만, 임베디드 시스템에서는 제한된 컴퓨팅 능력으로 인해 검출 속도가 느리다는 문제가 있다. 본 논문에서는 입력 영상에서 배경 부분을 빠르게 제거하여 검출 속도를 향상하는 방법과 ARM 아키텍처에서 NEON 병렬화 기법을 이용하여 검출 속도를 향상하는 방법을 제시한다. 제시한 방법으로 구현한 검출기는 기존보다 201.1% 향상된 속도를 나타냈다.

Delamination analysis of inhomogeneous viscoelastic beam of rectangular section subjected to torsion

  • Victor I. Rizov
    • Coupled systems mechanics
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    • v.12 no.1
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    • pp.69-81
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    • 2023
  • This paper considers a delamination analysis of a statically undetermined inhomogeneous beam structure of rectangular section with viscoelastic behavior under torsion. The beam is built in at its two ends. The beam has two longitudinal inhomogeneous layers with a delamination crack between them. A notch is made in the upper crack arm. The external torsion moment applied on the beam is a function of time. Under these conditions, the beam has one degree of indeterminacy. In order to derive the strain energy release rate, first, the static indeterminacy is resolved. Then the strain energy release rate is obtained by analyzing the balance of the energy with considering the viscoelastic behavior. The strain energy release rate is found also by analyzing the compliance of the beam for checkup. Solution of the strain energy release rate in a beam without a notch in the upper crack arm is derived too. In this case, the beam has two degrees of static indeterminacy (the torsion moment in the upper crack arm is treated as an additional internal redundant unknown). A parametric investigation of the strain energy release rate is carried-out.