• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.45.4-45
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• 2001

In this paper, we present the wet-based monitoring system for industrial controller such as inverter controller for hydraulic elevators. The monitoring system is using an embedded web server on embedded Linux platform. The control board of system-On-Chip (SoC) is based on ARM7TDMI with Ethernet controller. Wet-based monitoring system using embedded Linux platform can reduce the cost, and have flexibility both of technical issues and locations If the system to be monitored. The system shows the feasibility of remote monitoring system based on embedded Linux platform.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.137-140
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• 2003

대부분의 기존 임베디드 웹 서버 시스템은 어떤 특정 기기를 제어하기 위하여 고안되고 있다. 본 논문에서는 StrongArm 계열의 SA1110 chip을 채택하여 H/W 보드를 설계하고 최적의 웹 서버를 만들었다. 최근 널리 사용되고 있는 SA1110 H/W 보드 설계 중 Ethernet Controller인 CS8900A 설계에 관한 세부 사항들과 Ethernet 관련 Kernel patch에 대한 내용을 다루었다. 그리고 CS8900A에 대한 Network device driver 모듈에 대하여 자세히 언급하며, 제작된 보드를 사용하여 웹 서버 프로그램을 작성하여 MS 익스플로러 6.0환경에서 실험하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.389-396
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• 2003

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.664-670
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• 2018

In modern society, CCTV, which is the eye of surveillance, is being used to collect image data in various ways in daily life. CCTV is used not only for security, surveillance, and crime prevention but also in many fields such as automobile and black box. In this paper, we have developed a STM32F407 ARM chip based camera system for various applications. In order to develop camera system, modeling of camera system based on 3D structure was carried out in SolidWorks environment. The PCB board design was developed to extract the PCB parts from the camera system modeling files into iges files, convert them from the Altium Designer tool into 3D and 2D boards, After designing the camera system circuit and PCB, we have been studying the implementation of the stable system by using TRM (Thermal Risk Management) tool to cope with the heat simulation generated on the board.

• Journal of Biosystems Engineering
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• v.26 no.2
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• pp.163-168
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• 2001

A manipulator for test-cup attachment modules, which was a part of a robot milking system, was developed to reduce cost and labor for cow milking processing. A Cartesian coordinate manipulator was designed for the milking process, because it was quite flexible and can be constructed more economically than any other configuration. The manipulator was made use of DC motors, screws for power transmission, a RS422 interface system for the transmission of coordinate values and a one-chip microprocessor, 89C52. Performance tests of the manipulator were conducted to measure experimentally the precision of all axes. Some of the results are as follows. 1. The Cartesian coordinate manipulator was designed and built. Dimension of the three perpendicular axes (X, Y, and Z) and one arm’s axis(W) to pick up and transfer the modules were 700㎜$\times$450㎜$\times$550㎜$\times$650㎜. The arm’s axis moved the teat-cup attachment module, which attached four teat-cup to four teats, detached four teat-cup from four teats, was designed and manufactured by using CAD, CAM and CNC. 3. After 10 replications of exercising the manipulator, mean precision values(positioning error) of X, Y, Z axes wee 0.48㎜, 0.20㎜, 0.19㎜, respectively. Therefore, we conclude the axes to have a precision better than 0.5㎜, had no problem to operate correctly the milking manipulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

• Journal of IKEEE
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• v.21 no.4
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• pp.358-367
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• 2017

Advanced Driver Assistance Systems(ADAS), such as Front Collision Warning System (FCWS) are currently being developed. FCWS require high processing speed because it must operate in real time while driving. In addition, a low-power system is required to operate in an automobile embedded system. In this paper, FCWS is implemented in CPU-FPGA architecture in embedded system to enable real-time processing. The lane detection enabled the use of the Inverse Transform Perspective (IPM) and sliding window methods to operate at fast speed. To detect the vehicle, a Convolutional Neural Network (CNN) with high recognition rate and accelerated by parallel processing in FPGA is used. The proposed architecture was verified using Intel FPGA Cyclone V SoC(System on Chip) with ARM-Core A9 which operates in low power and on-board FPGA. The performance of FCWS in HD resolution is 44FPS, which is real time, and energy efficiency is about 3.33 times higher than that of high performance PC enviroment.