• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.167-170
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• 2018

본 논문에서는 바이너리 분석을 위한 ARM의 구조를 분석한다. 바이너리 분석이란 0과 1로 이루어진 이진 값의 의미를 분석하는 것을 말한다. 바이너리 코드를 역어셈블(Disassemble)하여 값으로만 존재하는 데이터가 어떤 명령어(Instruction)이며 어떤 피연산자(Operand)를 의미하는지 알 수 있다. 소스코드를 컴파일하여 실행파일이 생성이 되면 바이너리 값으로 구성되며 이 실행파일을 바이너리 파일이라고도 한다. 바이너리 파일을 분석하기 위해서 CPU의 명령어 집합 구조(Instruction Set Architecture)를 알아야 한다. PC와 서버, 모바일 등에서 많이 사용되고 있는 ARM 중에서 64비트를 지원하는 AArch64(ARMv8)의 명령어 구조를 분석하여 효율적인 바이너리 분석의 기반을 마련하고자 한다.

• Journal of the Korea Society of Computer and Information
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• v.17 no.11
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• pp.1-10
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• 2012

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.1-10
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• 2013

In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.5
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• pp.1233-1246
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• 2018

With the proliferation of smart mobiles, disassembly techniques for position-independent code (PIC) composed of ARM architecture instructions in computer security are becoming more important. However, existing techniques have been studied on x86 architecture and are focused on solving problems of non-PIC and generality. Therefore, the accuracy of the collected address information is low to apply to advanced security technologies such as binary measurement. In this paper, we propose a disassembly technique that reflects the characteristics of PIC composed of ARM instructions. For accuratly collecting traceable addresses, we designed value-set analysis having symbol-form domain. To solve the main problem of disassembly, we devised a heuristic using the characteristics of the code generated by the compiler. To verify the accuracy and effectiveness of our technique, we tested 669 shared libraries and executables in the Android 8.1 build, resulting in a total disassembly rate of 91.47%.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.18-20
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• 2000

디지털 음성통신을 위한 빠르고 쉬운 내장 프로세서(Embedded processor)가 요구되어짐에 따라 음성신호 압축 복원 알고리즘인 ADPCM과 LD-CELP의 구현에 가장 빈번히 사용되는 연산의 특성을 조사하였다. ARM6 processor core의 기본 구성요소들과 명령어집합을 기반으로 하여 음성부호화 알고리즘의 연산의 특성을 효율적으로 처리하기 위한 명령어와 구조를 추가한 범용 프로세서의 구조를 제안하고 VHDL로 기술하여 동작을 검증하였다. ARM6의 ALU logic에 leading zero count를 위한 회로를 추가하였고 opcode를 변경하였으며, LPC 계수 연산을 위해 제안된 MAC을 도입하여 효율적인 구현이 가능하도록 설계하였다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.1-11
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• 2006

In this paper, we propose a new register file architecture called the Register File Extension for Multi-words or Long-word Operation (RFEMLO) to accelerate both symmetric and asymmetric cryptographic algorithms. Based on the idea that most of cryptographic algorithms heavily use multi-words or long-word operations, RFEMLO allows multiple contiguous registers to be specified as a single operand. Thus, a single instruction can specify a SIMD-style multi-word operation or a long-word operation. RFEMLO can be applied to general purpose processors by adding instruction set for multi-words or long-word operands and functional units for additional instruction set. To evaluate the performance of RFEMLO, we use Simplescalar/ARM 3.0 (with gcc 2.95.2) and run detailed simulations on various symmetric and asymmetric cryptographic algorithms. By applying RFEMLO, we could get maximum 62% and 70% reductions in the total instruction count of symmetric and asymmetric cryptographic algorithms respectively. Also, performance results show that a speedup of 1.4 to 2.6 can be obtained in symmetric cryptographic algorithms and a speedup of 2.5 to 3.3 can be obtained for asymmetric cryptographic algorithms when we apply RFEMLO to a processor with an in-order pipeline. We also found that RFEMLO can effectively improve the performance of these cryptographic algorithms with much less cost compared to issue-width increase available in Superscalar implementations. Moreover, the RFEMLO can also be applied to Superscalar processor, leading to additional 83% and 138% performance gain in symmetric and asymmetric cryptographic algorithms.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.131-133
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• 2012

본 연구에서는 컴퓨터의 개념을 학부 신입생 교육과정에서 쉽게 이해할 수 있도록 ARM 명령어 집합의 부분 집합을 정의하고, 어셈블리 언어 코드를 입력받아 실행하는 가상 머신을 설계하고 구현하였다. 기존 교육 과정의 컴퓨터 구조 과목에서 다루는 어셈블리 언어는 실제의 머신을 기반으로 하기 때문에 개념을 학습하는데 있어서 불필요하게 복잡하다는 단점이 있다. 하지만 본 연구에서는 교육에 필요한 내용만을 포함한 가상 머신을 새롭게 정의함으로써 좀 더 우아한 방법으로 컴퓨터의 개념을 이해할 수 있도록 하였다. 특히 어셈블리 언어 학습을 통해서 컴퓨터 구조와 고급 언어 간의 상호작용을 이해하는데 도움이 될 수 있다. 제안한 가상 머신은 자바로 구현하였으며, 스캐너 및 파서를 구현하기 위해서 오픈소스 컴파일러-컴파일러 시스템을 사용하였다. 해당 가상 머신은 공과대학 학부 신입생을 위한 실습 프로그램으로 사용되었으며 컴퓨터 개념의 이해를 돕는데 유의미한 기여를 하였다.