• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.371-381
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• 2013

An encryption algorithm is executed to supply data confidentiality using a secret key which is embedded in a crypto device. However, the fault injection attack has been developed to extract the secret key by injecting errors during the encryption processes. Especially, an attacker can find the secret key of block cipher ARIA using about 33 faulty outputs. In this paper, we proposed a countermeasure resistant to the these fault injection attacks by checking the difference value between input and output informations. Using computer simulation, we also verified that the proposed countermeasure has excellent fault detection rate and negligible computational overhead.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.79-86
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• 2020

In this paper, we analyzed the case vulnerable to the power analysis attack of the ARIA algorithm and AES algorithm. Through this, we propose an algorithm with a safe structure for power analysis and prove through experiment. The proposed technique is a masking method using LFSR with a cyclic structure. To verify this, 1000, 2000, and 4000 power traces were collected, and the corresponding results are shown and proved. We used ATmega328 Chip for Arduino Uno for the experiment and mounted each algorithm. In order to measure the power consumption, a resistor was inserted and then proceeded. The analysis results show that the proposed structure has a safe structure for power analysis. In the future, we will study ways to lead to performance enhancement.

• International Journal of Internet, Broadcasting and Communication
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• v.8 no.1
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• pp.42-52
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• 2016

In this paper, we propose the 16-bits optimization design of the ARIA block-cipher algorithm for embedded systems with 16-bits processors. The proposed design adopts 16-bits XOR operations and rotated shift operations as many as possible. Also, the proposed design extends 8-bits array variables into 16-bits array variables for faster chained matrix multiplication. In evaluation experiments, our design is compared to the previous 32-bits optimized design and 8-bits optimized design. Our 16-bits optimized design yields about 20% faster execution speed and about 28% smaller footprint than 32-bits optimized code. Also, our design yields about 91% faster execution speed with larger footprint than 8-bits optimized code.

• Journal of the Korea Computer Industry Society
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• v.10 no.3
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• pp.105-114
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• 2009

In this paper a modified Feistel network 128 bit block cipher algorithm is proposed. The proposed algorithm has a 128, 196 or 256 bit key and it updates a selected 32 bit word from input value whole by deformed Feistel Network structure. Existing of such structural special quality is getting into block cipher algorithms and big distinction. The proposed block cipher algorithm shows much improved software speed compared with international standard block cipher algorithm AES and domestic standard block cipher algorithm SEED and ARIA. It may be utilized much in same field coming smart card that must perform in limited environment if use these special quality.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.6
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• pp.15-24
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• 2006

Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.629-630
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• 2006

This paper presented a hardware implementation of ARIA, which is Korean standard block ciphering algorithm. In this work, we proposed a improved architecture based on pipeline structure and confirmed that the design operates in a clock frequency of 101.7MHz and in throughput of 957Mbps in Xilinx FPGA XCV-1600E.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.585-592
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• 2014

In this paper, we study the LEA[1] block cipher system in UICC-16bit only. Also, we explain a key-schedule function and encryption/decryption structures, propose an advanced modified key-scheduling, and perform LEA in UICC-16bit that we proposed advanced modified key-scheduling. Also, we compare LEA with ARIA that proposed domestic standard block cipher, and we evaluate the efficiency on the LEA algorithm.

• Journal of the Korea Convergence Society
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• v.2 no.2
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• pp.13-19
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• 2011

When the existing mail system is attacked by the third party, its content is exposed fully. To solve this problem, designed is the mail encryption system which can send and receive mail safely by the sessionkey. The mail receiver opens encrypted mail with the session key. In the traditional mail system, the server administrator can view mail content. However, in the proposed protocol, the server can only save mail as encryption/decryption is applied. Also, the ARIA encryption algorithm is used in encryption/decryption for better safety, and fast XOR operations are used to reduce the amount of operations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.183-186
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• 2006

It is studied the implementation possibility of some encryption algorithms which meet the performance requirements in the smart card used in the TETRA system End-to-End Encryption. It is measured the operation time of the algorithm in the smart card which has 32 bit smart card controller made by Samsung Electronics. The algorithms used in the performance comparison are AES, ARIA, 3DES, SEED, IDEA which are the domestic or international standards. The input and output time of the smart card are measured using the smart card protocol analyzer. The pure algorithm operation time is calculated by the repeated algorithm operations. This measurement results can be used as the criteria for the selection of algorithm which will be used in the TETRA End-to-End encryption system. The algorithm which has better performance can be used for the implementation of additional functions in the smart lard, because of the enough time margin.