• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.10
• /
• pp.2261-2266
• /
• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Elastomers and Composites
• /
• v.51 no.3
• /
• pp.175-180
• /
• 2016

Influence of amino acidic chemical on properties of maleic anhydride-grafted ethylene-propylene-diene terpolymer/zinc oxide (EPDM-g-MAH/ZnO) composites was investigated. 4-Aminosalicylic acid (ASA), 4-amino-2-methoxybenzoic acid (AMBA), 12-aminolauric acid (ALA), and glutamine (Gln) were employed as the amino acidic chemicals. Though small quantity (0.5 phr) of the amino acidic chemical was added to the EPDM-g-MAH/ZnO composite, the properties were notably changed. By adding the amino acidic chemical, the percent crystallinity and apparent crosslink density were reduced. Order of the percent crystallinity was related to that of the $pK_a$ values of amino acidic chemicals. By adding the amino acidic chemical, the basic tensile properties were on the whole improved. The experimental results were explained by the $pK_a$ values of amino acidic chemicals, change of zinc ionomer formation, and interactions between the additive and EPDM-g-MAH chain.

• Journal of Institute of Control, Robotics and Systems
• /
• v.20 no.4
• /
• pp.474-479
• /
• 2014

LEON3 is a 32-bit synthesizable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7- stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the debugging tool for LEON3 based embedded systems. The debugging tool can initialize the target hardware, find out how the target hardware is configured, load application code to a specified memory space and run that application code. To provide users a debugging environment, it can set breakpoints and control the operation of LEON3 correspondingly. And function call trace is one of key functions of the debugging tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.100-103
• /
• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.112-115
• /
• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Journal of KIISE:Computer Systems and Theory
• /
• v.35 no.6
• /
• pp.284-292
• /
• 2008

The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.9
• /
• pp.2009-2014
• /
• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance comparison of TDMA and Lottery bus arbitration policy developed recently due to farious conditions and propose the methods of performance improvement.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.12
• /
• pp.2647-2654
• /
• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.8
• /
• pp.1879-1884
• /
• 2013

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.9A
• /
• pp.868-873
• /
• 2010

H.264/AVC video compression standard has been adopted for DMB, digital TV and various next generation broadcasting, communication and consumer electronics applications, and modern DVR system is also based on H.264/AVC standard. Although PC-based DVRs use PCI bus for main interface typically, H.264/AVC codec for SOCs use AHB bus for host interface. In this paper, we present an implementation of PCI to AHB interface module for H.264/AVC codec to efficiently communicate with a PC and experimental results.