• Journal of Power Electronics
• /
• v.16 no.1
• /
• pp.190-204
• /
• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• Journal of Power Electronics
• /
• v.14 no.2
• /
• pp.402-412
• /
• 2014

This paper proposes a novel electric propulsion system for naval ships, which consists of Active Front End (AFE) converters directly connected to battery Energy Storage Modules (ESMs). Employing the proposed AFE converters with ESMs in the power systems of naval ships can enhance the reliability and quality of the electric power. Furthermore, the fuel-efficiency of the generator can be improved by a higher loading factor of the generator and its prime movers. The proposed AFE configuration does not require an additional dedicated DC/AC converter for the ESMs. Instead of that, the AFE converter itself can control the DC link voltage and the discharging and/or charging of the ESMs. A control scheme to achieve these control objectives is also presented in this paper. The overall power system, including the generators and electrical loads of a naval ship, is implemented by a small scaled Power Hardware-In-the-Loop (PHIL) simulator. Through this experimental setup, the proposed system configuration and the power control strategies are verified. It is shown that the fuel-efficiency and transient dynamics can be improved in the normal and contingency operation modes.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.2
• /
• pp.109-117
• /
• 2017

This paper describes the design and implementation of a unit module for a 10 kVA class 13.2 kV/220 V unidirectional solid-state transformer (SST) with silicon-carbide metal-oxide-semiconductor field-effect transistors. The proposed module consists of an active-front-end (AFE) converter to interface 1320 V AC voltage source to 2500 V DC link and an isolated resonant DC-DC converter for 500 V low-voltage DC output. The design approaches of the AFE and the isolated resonant DC-DC converters are addressed. The control structures of the converters are described as well. The experiments for the converters are performed, and results verify that the proposed unit module can be successfully adopted for the entire SST operation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.31-39
• /
• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.23 no.2
• /
• pp.121-128
• /
• 2018

This work proposes a simple control method of a buck-type active power decoupling circuit that can minimize the ripple values in the dc link voltage. The proposed method utilizes a simplified duty calculation method and an optimal compensation gain tracking algorithm with variable-step approach. Thus, the dc link voltage ripple can be effectively reduced through the proposed method along with rapid response in tracking the optimum compensation gain. Moreover, the proposed method has better dynamic responses in the load fluctuation or abnormal situation. MATLAB/Simulink simulation and hardware-in-the-loop-simulation(HILS)-based experimental results are presented to validate the effectiveness of the proposed control method.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.212-213
• /
• 2017

In this paper is presented a pre-charging sequence for single-phase cascaded neutal-point-clamped(NPC) converters for capacitors voltage balancing. capacitor imbalance problem in pre-charge sequence is caused in cascaded NPC converter by its topology. the DC link voltage at each NPC converter module can be balanced by the proposed switching method. the design and performance of the proposed sequence are verified by simulation and experimental results using prototype.