• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.1032-1040
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• 2010

This paper describes implementation of electonic seal (E-Seal) of a container based on ISO 18185 standard and development of monitoring systems checking E-Seal device and cargo states in the container for secure transportation from departure to destination. For lack of definition on confidentiality support in ISO 18185-4 standard, it is vulnerable to security attack such as sniffing. To cope with this, we developed encryption/decryption functions implementing RC5 and AES-128 standards and compared their performance. Experimental results showed that RC5 outperformed AES-128 in terms of time delay. In addition, RC5 had an advantage under the condition of large sized messages as well as CPUs with low performance. However, the portion of encryption/decryption processing time was less than 1 percent of response time including communication delay between E-Seal tags and readers. Hence, the performance difference between RC5 and AES-128 standards was trivial, which revealed that both specifications were allowable in developed systems.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.1
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• pp.1-9
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• 2022

Fixslicing AES is a technique that omits the Shiftrows step to minimize the cost of the linear layer of Bitsliced AES, showing a 30% performance over the Bitsliced technique. However, the amount of code increases to compensate for the omitted shiftrows. Therefore, it is proposed to be divided into Semi-Fixsliced in which only half of shiftrows are omitted and Fully-Fixsliced in which Shiftrows are omitted completely. In this paper, we propose a CTR mode implementation of Fixslicing AES on RISC-V using the pre-computed table technique. By utilizing the characteristics of the CTR mode, it is possible to perform fast encryption by omitting up to the second round SubBytes from the encryption process through pre-computed up to the second round SubBytes operation. Using this technique, it was confirmed that Semi-Fixsliced has a performance of 1,345 cycles per block and a performance improvement of 7% compared to the previous performance result, and Fully-Fixsliced has a performance of 1,283 cycles per block and a performance of 9% compared to the previous performance result on 32-bit RISC-V.

• Journal of Internet Computing and Services
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• v.22 no.5
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• pp.17-26
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• 2021

This paper is about a physical layer frame security technique using OFB-style encryption/decryption with AES algorithms on Gigabit Ethernet network. We propose a data security technique at the physical layer that performs OFB-style encryption/decryption with AES algorithm with strong security strength when sending and receiving data over Gigabit Ethernet network. Generally, when operating Gigabit Ethernet network, there is no security features, but data security is required, additional devices that apply this technique can be installed to perform security functions. In the case of data transmission over Gigabit Ethernet network, the Ethernet frames conform to IEEE 802.3 specification, which includes several fields to ensure proper reception of data at the receiving node in addition to the data field. When encrypting, only the data field should be encrypted and transmitted in real time. In this paper, we show that only the data field of the IEEE802.3 frame is encrypted and transmitted on the sending node, and only the data field is decrypted to show the plain text on the receiving node, which shows that the encryption/decryption is carried out correctly. Therefore, additional installation of devices that apply this technique can increase the reliability of the system when security for data is required in Ethernet network operating without security features.

• Journal of information and communication convergence engineering
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• v.12 no.4
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• pp.252-256
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• 2014

Traditional block cipher Advanced Encryption Standard (AES) is widely used in the field of network security, but it has high overhead on each operation. In the 15th international workshop on information security applications, a novel lightweight and low-power encryption algorithm named low-power encryption algorithm (LEA) was released. This algorithm has certain useful features for hardware and software implementations, that is, simple addition, rotation, exclusive-or (ARX) operations, non-Substitute-BOX architecture, and 32-bit word size. In this study, we further improve the LEA encryptions for cloud computing. The Web-based implementations include JavaScript and assembly codes. Unlike normal implementation, JavaScript does not support unsigned integer and rotation operations; therefore, we present several techniques for resolving this issue. Furthermore, the proposed method yields a speed-optimized result and shows high performance enhancements. Each implementation is tested using various Web browsers, such as Google Chrome, Internet Explorer, and Mozilla Firefox, and on various devices including personal computers and mobile devices. These results extend the use of LEA encryption to any circumstance.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.934-936
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• 2004

본 논문의 목적은 AES(Advanced Encryption Standard)로 선정된 Rijndael 암호 및 복호 알고리즘을 하드웨어로 설계하고 이를 저비용의 FPGA로 구현하는 것이다. 설계된 AES 암호프로세서는 20만 게이트 급 이하의 FPGA로 구현한다는 비용의 제약 조건 하에서 대용량의 데이터를 암호화, 복호화 하기에 적합한 성능을 가지도록 하였다. 또한 구현 단계에서는 설계한 AES 암호프로세서와 UART 모듈을 동일 FPGA상에서 통합하여 실용성 및 면적 효율성을 보였다. 구현된 Rijndael 암호 프로세서는 20만 게이트를 갖는 Xilinx사의 Spartan-II 계열의 XC2S200 칩 사용시 53%의 면적을 차지하였고, Static Timing Analyzer로 분석한 결과 최대 29.3MHz 클럭에서 동작할 수 있고 337Mbps의 최대 성능을 가진다. 구현된 회로는 실제 FPGA를 이용하여 검증을 수행하였다.

• ETRI Journal
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• v.33 no.3
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• pp.434-442
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• 2011

This paper presents a practical differential fault analysis method for the faulty Advanced Encryption Standard (AES) with a reduced round by means of a semi-invasive fault injection. To verify our proposal, we implement the AES software on the ATmega128 microcontroller as recommended in the standard document FIPS 197. We reduce the number of rounds using a laser beam injection in the experiment. To deduce the initial round key, we perform an exhaustive search for possible key bytes associated with faulty ciphertexts. Based on the simulation result, our proposal extracts the AES 128-bit secret key in less than 10 hours with 10 pairs of plaintext and faulty ciphertext.

• Annual Conference of KIPS
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• 2019.05a
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• pp.125-128
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• 2019

최근 사물인터넷 기술의 발전과 함께 하드웨어 디바이스에서 측정하는 센싱 데이터를 보호하기 위해 다양한 방식의 암호화 알고리즘을 채택하고 있다. 그 중 전 세계에서 가장 많이 사용하는 암호화 알고리즘인 AES(Advanced Encryption Standard) 또한 강력한 안전성을 바탕으로 많은 디바이스에서 사용되고 있다. 하지만 AES 알고리즘은 DPA(Differential Power Analysis), CPA(Correlation Power Analysis) 같은 부채널 분석 공격에 취약하다는 점이 발견되었다. 본 논문에서는 부채널 분석 공격대응방법 중 가장 널리 알려진 마스킹 기법을 적용한 AES 알고리즘의 소프트웨어 최적화 구현 기법을 제시한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2203-2208
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• 2011

In this paper, we describe application service development for secure land and marine transport based on CSD (Conveyance Security Device) systems. Based on CSD systems, we present application service and security service according to relevant standards as well as test procedure of developed services. Exploiting temperature, moisture, impact sensors, state monitoring function of container freight was developed to prevent disaster during transportation in addition to security function with CSD. For confidentiality of messages exchanged among application service entity and CSD systems, Encryption and decryption functions going by RC5 and AES-128 algorithms were implemented at desktop PC and 8 bit CPU environments, respectively. Measuring the elapsed time during encryption and decryption shows that two algorithms are allowable for the application service.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.940-943
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• 2002

This paper presents hardware implementations of the two representative cryptographic algorithms, Advanced Encryption Standard (Rijndael), and the present American federal standard (Triple DES) using a PCI- based FPGA board named "EBSW-1" This board bases on a FPGA chip (Xilinx Virtex300 XCV300PQ240-4). The implementation results of these two algorithms were tested successfully. AES circuit could proceed an encryption as well as a decryption two times faster than the Triple-DES circuit, while the former circuit used higher rates of CLBs. Besides, if these architectures use pipeline-registers, the processing speed will be increased about 1.5 times than the presented circuits.