• Progress in Medical Physics
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• v.21 no.1
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• pp.70-77
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• 2010

This study tested how S/N (Signal to Noise Ratio) ratios and ADC (apparent diffusion coefficient) values vary with different T-scores in a group of patients with osteoporosis. Based on DEXA (Dual Energy X-ray Absorptiometry) T-scores for L1.L4 for two groups of subjects consisting of 30 healthy people without osteoporosis and 30 patients who came for treatment of waist (lumbar or low back) pain and were suspected to have osteoporosis as judged from the simple X-ray findings, this study classified every spine into two groups of osteoporosis and osteopenia. Signal intensity measurements were made in the four regions of L1 to L4 on diffusion-weighted MR images obtained using 1.5T MR scanner, while ADC measurements were obtained from ADC map images. As an approach for quantitative analysis, the comparison of the variances in S/N ratios and ADC values for varying T-scores in the selected regions of interest was carried out based on averaged T-scores, S/N ratios, and ADC values. Also, the variances in S/N ratios and ADC values for each of the groups of osteoporosis and osteopenia, which were classified into by T-scores, were compared. For qualitative analysis, a careful naked eye examination of signal intensity differences in the area of L4 was made on T1-weighted sagittal images for each of the healthy (normal), osteopenia, and osteoporosis groups. In the qualitative analysis, it was found that for both the osteopenia group and the osteoporosis group, as T-scores deceased, the S/N ratios on diffusion-weighted MR images also decreased, with the greatest decrease in the S/N ratio found in the osteoporosis group. Additionally, among the three groups, the lowest S/N ratio was found in the osteoporosis group. With respect to ADC map, it was found that for both the osteopenia group and the osteoporosis group, as T-scores deceased, the ADC values on diffusion-weighted MR images also decreased, with the greatest decrease in the ADC values found in the osteoporosis group. Additionally, among the three groups, the lowest ADC value was found in the osteoporosis group. On the other hand, in the qualitative analysis, the osteoporosis group showed the highest signal intensity. Additionally, among the three groups, the lowest signal intensity was found in the healthy (normal) group. It was found that as osteoporosis progressed, S/N ratio and ADC decreased, whereas signal intensity increased on T1-weighted images. Also, in diagnosing osteoporosis, MRI tests turned out to be (more) effective.

• Journal of Korea Foundry Society
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• v.32 no.3
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• pp.157-164
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• 2012

• Journal of Ginseng Research
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• v.13 no.2
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• pp.229-233
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• 1989

The effect of some phytohormones and light on the growth, ADC activity and polyamine content in ginseng was studies. In seedlings, the growth, ADC activity and putrescine content were in creased by Ghs treatment. ADC activity ann putrescine content were slightly slightly derreased by ABA, but not changed by kinetin. Light treatment increased ADC activity and putrescine content greatly. In two year ginseng leaves treated by GA3, the ADC actin$.$its reached maximum and the spermidine content reached maximum 2 days faster than in the control. Thtse results suggest the possibility that these regulators are closely related to growth and polyamine cotent. UeVo'ordsEPanaxgineng C.A. Meyer, Polyamine, Putrescine spermidine, arginine decarboxylose, GA3 kiiletin , ABA.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.583-586
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• 2001

본 논문에서는 다중 대역통과 표본화 이론에 기반하여 1.9GHz IS-95신호와 2.2GHz IMT-2000 신호를 하나의 ADC(analog to digital converter)를 사용하여 동시에 표본화하고 디지털 처리를 수행하는 방법을 제안하고 실험을 통하여 검증하였다. 일반적인 방법으로는 본 논문에서 고려하는 두 신호를 동시에 표본화하기 위해서는 표본화 주파수가 최소한 1GHz 이상의 고속의 ADC를 사용해야 한다. 그러나 현재 ADC의 기술은 광대역의 신호를 직접 더지털화하기에는 아직 미흡하다. 반면에 대역통과 표본화 이론은 기존의 상용 ADC와 기콘의 RF 시스템을 이용하여 다른 대역에 위치한 두 신호를 통합처리 할 수 있는 기반을 제공하고 있다. 본 논문에서는 이러한 대역통과 표본화 이론에 기반을 두고 상용 ADC를 사용하여 표본화 시스템을 구현하여 IS-95신호와 IMT-2000 신호를 표본화하고 이를 컴퓨터에서 디지털 필터를 이용하여 두 신호를 분리하는 실험을 통하여 다중 대역통과 표본화의 적용 가능성을 검증하였다.

• International Journal of Internet, Broadcasting and Communication
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• v.5 no.2
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• pp.11-14
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• 2013

This paper describes the sigma-delta ADC/DAC digital block with two channels. The ADC block has comb filter and three half band filters. And the DAC block has 5th Cascaded-of-Integrators Feedback DSM. The ADC and DAC support I2S, RJ, LJ and selectable input data modes of 24bit, 20bit, and 16bit. It is fabricated with 0.35um Hynix standard CMOS cell library. The chip size is 3700*3700um. It has been verified using NC Verilog Simulator and Matlab Tool.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.955-958
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• 2003

본 논문에서는 개방형 파이프라인 구조를 이용한 8비트 500Msamples/s ADC를 제안하였다. 8-비트의 해상도에 적합하면서 전력 소모가 적은 5 단 파이프라인 구조로 설계하였으며, 고속 동작에 적합하게 MUX 스위치에서 선택한 신호를 인터폴레이션하는 개방형 구조를 채택하였다. 전력 소모와 전체 칩 면적을 줄이기 위해서, 각 단에서 필요한 신호의 수를 줄이도록 설계하였다. 설계된 ADC 는 3 개의 신호를 이용하여 구현 함으로서 각 단에서의 증폭기 수틀 줄일 수 있었다. 또한 1.8V 의 낮은 전원 전압에 의한 작은 입력 범위에서 8-비트의 해상도를 만족하기 위해서 Offset Cancellation 기법을 사용하였다. 제안된 ADC 는 0.18μ m 일반 CMOS 공정을 이용하여 설계되었으며 시뮬레이션 결과 500Msamples/s에서 220mW의 전력 소모를 가지며, 1.2Vp-p (Differential) 입력 범위에 대해서 약 48dB의 SNDR을(8-비트의 해상도) 가짐을 확인할 수 있었다.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.295-301
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• 2012

In this article, we have designed SHA, which has 12 Bit resolution at an input signal range of 1 $V_{pp}$ and operates at a sampling speed of 100 MS/s in order to use at front of high speed ADC. SFDR(Spurious Free Dynamic Range) of the proposed system drops to approximately 66.3 dB resolution when the input frequency is 5 MHz, and the sampling frequency is 100 MHz, however, the circuit without a feedthrough has 12 bit resolution with approximately 73 dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.467-474
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• 1990

In this paper, the circuit that has characteristics of high speed and low dissipation is described. A 4:1 parallel ADC is constructed by using the designed SCFL(Source Coupled FET Logic). The results of simulation shows that comparators is obtained integrated nonlinearity, $\pm$28mV, compared with limiting value, $\pm$68mV, at 66NHz input signal and 2Gs/s Niquist rates and this paper describes low power dissipation about 0.43W by reducing the elements in a ADC design.