• 제목/요약/키워드: AA1050

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Octadecylviologen-TCNQ LB 막의 물리적 특성 (Physical Properties of the Langmuir-Blodgett Films Layered with Octadecylviologen-TCNQ)

  • 신동명;박제상;강도열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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    • pp.77-80
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    • 1995
  • Enhancing the electrical conductivity of the ultrathin organic films using Langmuir-Blodget technique is important step for the developement of molecular electronic device. The Octadecylviologen-TCNQ was synthesized with Octadecylviologen-Bromide an Lithium TCNQ Sine Octadecylviologen-TCNQ has two TCNQ snion radicals, the conductivity of LB film is expected to increase. The $\pi$-A isotherm showed that the limiting area was 150${\AA}$$\^$2/ molecule and the silid-like transition surface pressure was 25 mN/m. The electronic transition of the TNCNQ anion radical was observed at 400 nm. Intermolecular charge transfer absorption was observed at 600nm and 850~1050 nm which ay resulted from the TCNQ anion radical dimer formation. The electrical conductivity of the viologen -TCNQ LB film was 10$\^$-6/cm This values was 100 times higher than that of the quinolinium-TCNQ and pyridinium-TCNQ LB films.

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급속 건식 열산화 방법에 의한 초박막 SiO2의 성장과 특성 (Growth and Properties of Ultra-thin SiO2 Films by Rapid Thermal Dry Oxidation Technique)

  • 정상현;김광호;김용성;이수홍
    • 한국전기전자재료학회논문지
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    • 제17권1호
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    • pp.21-26
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    • 2004
  • Ultra-thin silicon dioxides were grown on p-type(100) oriented silicon employing rapid thermal dry oxidation technique at the temperature range of 850∼1050 $^{\circ}C$. The growth rate of the ultra-thin film was fitted well with tile model which was proposed recently by da Silva & Stosic. The capacitance-voltage, current-voltage, characteristics were used to study the electrical properties of these thin oxides. The minimum interface state density around the midgap of the MOS capacitor having oxide thickness of 111.6 $\AA$ derived from the C-V curve was ranged from 6 to 10${\times}$10$^{10}$ /$\textrm{cm}^2$eV.

냉간 대칭/비대칭 압연시 압연변형율 상태와 집합조직의 형성 (Evolution of Strain States and Textures During Symmetrical/Asymmetrical Cold Rolling)

  • 허무영;이재필;이재협
    • 한국소성가공학회:학술대회논문집
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    • 한국소성가공학회 2004년도 제5회 압연심포지엄 신 시장 개척을 위한 압연기술
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    • pp.19-24
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    • 2004
  • Symmetrical and asymmetrical rolling was performed in AA 1050 sheets. Asymmetrical rolling was carried out by using different roll velocities of upper and lower rolls. The effect of the reduction per rolling pass on the formation of textures and microstructures during symmetrical and asymmetrical rolling was studied. In order to intensify the shear deformation, symmetrical and asymmetrical rolling was carried out without lubrication. The strain states associated with rolling were investigated by simulations with the finite element method (FEM). A fairly homogeneous residual shear strain throughout the sheet thickness was observed after asymmetrical rolling. Symmetrical rolling with a high friction gave rise to a strong net shear strain gradient in the sheet thickness.

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후막 GaN특성에 관한 연구 (A Study on the Thick GaAN Properties)

  • 송복식;정성훈;김영호;홍필영;문동찬;김선태
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1996년도 춘계학술대회 논문집
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    • pp.19-22
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    • 1996
  • GaN films were prepared on Al$_2$O$_3$(1120) substrates by hydride vapor phase epitaxy (HVPE) with HCl-NH$_3$-N$_2$ gas system. The growth rate was increased with increasing the substrate temperature below 1050$^{\circ}C$ and decreased over the temperature, increased with growth time. The X-ray diffraction patterns showed only (0002) GaN peak. The UV-Visible Spectrophotometer showed a good optical absorption and fundamental absorption occurred at 3700${\AA}$.

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새로운 증착원으로 형성된 MOCVD TiN에 관한 연구 (Formation of MOCVD TiN from a New Precursor)

  • 최정환;이재갑;김지용;이은구;홍해남;신현국
    • 한국재료학회지
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    • 제9권3호
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    • pp.244-250
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    • 1999
  • 새로운 TiN 선구체인 TEMAT(tertrakis etylmethylamino titanium)과 암모니아를 이용하여 TiN 박막을 형성하였다. 단일 증착원으로 증착시킨 경우에는 $70~1050\AA$/min의 증착률을 얻을 수 있었으며 증착온도에 지배를 받았다. $275^{\circ}C$의 증착온도에서 $0.35\mu\textrm{m}$의 접촉창에서 약 90%의 도포성을 얻을 수 있었다. TEMAT에 암모니아를 첨가하였을 때 단일증착원에서 $3500~6000\mu\omega-cm$정도의 갑을 나타내던 비저상이 ~$800\mu\omega-cm$ 정도로 낮아졌으며 대기중 막의 안정성도 향상되었다. AES의 분석결과에서도 암모니아의 첨가로 현저한 산호와 탄소 함량의 감소를 나타내었다. 그러나 암모니아의 유량을 증가시킬수록 $0.5\mu\textrm{m}$ 접촉창에서 나타난 tiN 박막의 도포성은 감소하였고 이는 TEMAT와 암모니아의 기상 반응에의한 높은 첩착계수를 가진 중간 생성물의 형성에 의한 것으로 생각된다. 반응 부산물에 대한 분석은 QMS에 의해 이루어 졌으며 transamination 반응에 의한 TiN 증착 기구를 제시하였다. 추가적으로 XPS 분석으로 TEMAT와 암모니아의 반응에 의해 만들어지는 탄소는 금소기 탄소였으며 $\beta$-수소 반응이 transamination 반응과 경쟁적으로 일어남을 나타내었다.

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NMOSFET에서 LDD 영역의 전자 이동도 해석 (Analysis of electron mobility in LDD region of NMOSFET)

  • 이상기;황현상;안재경;정주영;어영선;권오경;이창효
    • 전자공학회논문지A
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    • 제33A권10호
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    • pp.123-129
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    • 1996
  • LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

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등통로각압축 공정용 저하중 분리형 금형 설계 (Split Die Design for ECAP with Lower Loads)

  • 진영관;강성훈;손일헌;임용택
    • 대한기계학회논문집A
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    • 제32권3호
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    • pp.217-222
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    • 2008
  • Equal channel angular pressing (ECAP) is one of the effective methods to produce bulk-nano materials by accumulating plastic strain into the workpiece without changing its cross-sectional shape in the multi-pass processing. However, the forming load becomes higher for manufacturing large specimens using conventional solid or split dies because of friction, flash formation, and usage of dummy specimen. In the present investigation, better split die was designed to reduce the forming loads and improve the geometrical accuracy of the specimen in the multi-pass ECAP. The new die exit channel was also designed to reduce the friction effect. Experiments with AA1050 specimens with a square cross-section were carried out to examine the design goal using the proposed split dies for routes A and C up to four passes. The numerical forming simulations were used to determine the effective geometry of various die models in the present work.

텅스텐 실리사이드 열처리 거동에 미치는 계면 효과 (Interface effects on the annealing behavior of tungsten silicide)

  • 진원화;오상헌;이재갑;임인곤;김근호;이은구;홍해남
    • 한국표면공학회지
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    • 제30권6호
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    • pp.374-381
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    • 1997
  • We have studied the effect of the interface between tungsten silicide and polysilicon the silicide reaction. The results showed that the cleaning of the silicon surface prior to the deposition of tungsten silicide affected the interface properties, thereby leading to the difference in the resistivity and surface morhpology of tungsten silicide. Compared with HF cleaning, the use of SCl cleaning yielded higher resistivity of tungsten silicide at the low anneal temperature (up to $900^{\circ}C$). However, furtherature to $1000^{\circ}C$ reduced the resistivity significantly, similar to that obtained with HF cleaning. It was also observed that the annealing of WSix/HF-cleaned poly-si allowed the formation of bucking weve (partially decohesion area) on the surface. In contrast, the use of SCl celaning did not produce the buckling waves on the surface. Also the presence of 200$\AA$ -thick TiW between tungsten silicide and HF-cleaned poly-Si effectively prevented the formation of the waves. However, high-temperature annealing of WSix/200A-TiW/Poly-Si allowed the excess silicon in tungsten silicide to precipitate inside the silcide, causing the slight increase of the resistivity after annealing at $1050^{\circ}C$.

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Total Fiber-to-fiber Insertion Loss가 <6dB 인 Ti:$LiNbO_3$ 과도파로 Pigtailing 및 손실분석 (The Pigrailing and The Loss Analysis of low loss LiNbO$_3$ Optical Waveguide with Fiber-to-fiber Insetion Loss<6dB)

  • 김성구;박계춘;조재철
    • 한국전기전자재료학회논문지
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    • 제11권7호
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    • pp.557-564
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    • 1998
  • A low loss x-cut $LiNbO_3$optical waveguide was fabricated by Yi in-diffusion, and the properties of guided-mode and the total insertion loss of the pigtailed waveguide with polarization maintaining fiber(PMF) were measured at optical wavelength 1550nm. for forming the waveguides, the parameters of diffusion, Ti thickness, waveguide line-width, length, diffusion temperature, time and atmosphere were set $1400{\AA}$, $8{\mu}m$, 3.3cm, $1050^{\circ}C$, 8 hours and wet bubbled oxygen, respectively. And then after the polishing and piatailing, it showed that the total insertion loss was -4.1dB for TM mode, -5.5dB for TE mode, and mode size, that is, the horizontal/ vertical size were $13.8{\mu}m/18{\mu}m$ for TM mode, $9.6{\mu}m/6.5{\mu}m$ for TE mode.

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승온중 수소 분위기 제어에 의한 선택적 Si 에피텍시 성장 (Selective Si Epitaxial Growth by Control of Hydrogen Atmosphere During Heating-up)

  • 손용훈;박성계;김상훈;남승의;김형준
    • 한국재료학회지
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    • 제12권5호
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    • pp.363-368
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    • 2002
  • we proposed the use of $Si_2H_ 6/H_2$ chemistry for selective silicon epitaxy growth by low-pressure chemical vapor deposition(LPCVD) in the temperature range $600~710^{\circ}C$ under an ultraclean environment. As a result of ultraclean processing, an incubation period of Si deposition only on $SiO_2$ was found, and low temperature epitaxy selective deposition on Si was achieved without addition of HCI. Total gas flow rate and deposition pressure were 16.6sccm and 3.5mtorr, respectively. In this condition, we selectively obtained high-quality epitaxial Si layers of the 350~1050$\AA$ thickness. In older to extend the selectivity, we kept high pressure $H_2$ environment without $Si_2H_6$ gas for few minutes after first incubation period and then we conformed the existence of second incubation period.