• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.9
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• pp.347-354
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• 1984

This paper presents a method of improving the power factor and , the waveform of A.C line currents and the output waveforms of AC to DC fully bridge converter systems which is achieved by connecting CON I.II and CON III.IV in series and parallel. The basic principle of the CON I.II.III.IV's operation is simple and feasibility of thease converter is proved by experiments. CON I and CON III are constructed of natural commutation, CON II and CON IV are constructed of forced commutation. The experimental results show that the power factor and waveform of the source currents and the output waveforms are improved by the method of connecting converter in series and parallel and driving it in I, II, III, IV quadrant.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.95-101
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• 2022

The two-sided assembly line balancing problem is a kind of NP-hard problem. This problem primarily can be solved metaheuristic method. This paper suggests parallel clustering algorithm that each left and right-sided workstation assigned by operations with T_i = c^* ± α < c, c^* = ${\lceil}$W/m^*${\rceil}$ such that M^* = ${\lceil}$W/c${\rceil}$ for precedence diagram of two-sided assembly line with total complete time W and cycle time c. This clustering performs forward direction from left to right or reverse direction from right to left. For the 4 experimental data with 17 cycle times, the proposed algorithm can be obtain the minimum number of workstations m^* and can be reduce the cycle time to T_max < c then metaheuristic methods. Also, proposed clustering algorithm maximizes the line efficiency and minimizes the variance between workers operation times.

• Journal of Power Electronics
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• v.13 no.4
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• pp.507-515
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• 2013

This paper presents an isolated bidirectional dc/dc converter based on primary parallel isolated boost converter (PPIBC). This topology is an efficient solution in low voltage high power applications due to its ability to handle high currents in the low voltage side. In this paper, the converter has been modeled using non-ideal components and operated without any additional circuitry for startup using a digital soft-start procedure. Simulated and measured loop gains have been compared for the validity of the model. On-the-fly current direction change has been achieved with a prototype interconnecting two battery banks. A second prototype has been constructed and tested for supercapacitor operation in constant power charge mode.

• Progress in Superconductivity
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• v.5 no.1
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• pp.45-49
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• 2003

We have designed and fabricated the single-layer high $T_{c}$ SQUID magnetometer consisting of a directly coupled grain boundary junction SQUID with an inductance of 100 pH and 16 nested parallel pickup coils with the outermost dimension of 8.8 mm ${\times}$ 8.8 mm. The magnetometer was formed from a YBCO thin film deposited on an STO(100) bicrystal substrate with a misorientation angle of $30^{\circ}$. The SQUID magnetometer was further improved by optimizing the multi-loop pickup coil design for use in unshielded environments. Typical characteristics of the dc SQUID magnetometer had a modulation voltage of 40 $\mu\textrm{V}$ and a white noise of $30fT/Hz^{1}$2/. The SQUID magnetometer exhibited a 1/f noise level at 10 Hz reduced by a factor of about 3 compared with that of the conventional solid type pickup coil magnetometers and a very stable flux locked loop operation in magnetically disturbed environments.s.

• MALSORI
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• no.52
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• pp.111-120
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5 kbytes for program code. Maximum required time of 29.2 ms for processing a frame of 32 ms of speech validates real-time operation of the implemented system.

• Journal of Power Electronics
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• v.13 no.3
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• pp.329-338
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• 2013

In this paper, the charging characteristics of series resonant type high voltage capacitor chargers considering the transformer stray capacitance have been studied. The principles of operation for the four operational modes and the mode changes for the four different switching frequency sections are explained and analyzed in the range of switching frequency below the resonant frequency. It is confirmed that the average charging currents derived from the above analysis results have non-linear characteristics in each of the four modes. The resonant current, resonant voltage, charging current, and charging time of this capacitor charger as variations of the switching frequency, series parallel capacitance ratio ($k=C_p/C_s$), and output voltage are calculated. From the calculation results, the advantages and disadvantages arising from the parallel connection of this stray capacitance are described. Some methods to minimize charging time of this capacitor charger are suggested. In addition, the results of a comparative test using two transformers whose stray capacitances are different are described. A 1.8 kJ/s prototype capacitor charger is assembled with a TI28335 DSP controller and a 40 kJ, 7 kV capacitor. The analysis results are verified by the experiment.

• Journal of computational fluids engineering
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• v.17 no.4
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• pp.1-8
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• 2012

During a reactor normal operation, two parallel 50% capacity cooling pumps circulate primary coolant to remove the fission reaction heat of the reactor through heat exchangers cold by a cooling tower. When one pump is failure, the other pump shall continuously circulate the coolant to remove the residual heat generated by the fuels loaded in the reactor after reactor shutdown. It is necessary to estimate how much flow rate will be supplied to remove the residual heat. We carried out a flow network analysis for the parallel primary pumps based on the piping network of the primary cooling system in HANARO. As result, it is estimated that the flow rate of one pump increased about 1.33 times the rated flow of one pump and was maintained within the limit of the cavitation critical flow.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.291-291
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• 2000

A vehicle driving simulator is a virtual reality device which a human being feels as if the one drives a vehicle actually. Driving Operation System acts as an interface between a driver and a driving simulator. This paper suggests the driving operation system for a driving simulator. This system consists of a controller, DC geared motor, MR brake, rotary encoders, steeping motor and bevel gear box. Reaction force and torque on the steering system were made by DC_Motor and MR_Brake. Reaction force and torque on the steering system were compare between real car and a driving simulator. The controller based on the 80C196KC micro processor that manage and transfer signal.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.49-57
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• 2002

In this paper, we deal with a real time implementation of the integrated image-based navigation parameter extraction system using the TMS320C80 MVP(multimedia video processor). Our system consists of relative position estimation and absolute position compensation, which is further divided into high-resolution aerial image matching, DEM(Digital elevation model) matching, and IRS (Indian remote sensing) satellite image matching. Those algorithms are implemented in real time using the MVP. To achieve a real-time operation, an attempt is made to partition the aerial image and process the partitioned images in parallel using the four parallel processors in the MVP. We also examine the performance of the implemented integrated system in terms of the estimation accuracy, confirming a proper operation of the our system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.59-70
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• 2007

In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.