• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06b
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• pp.133-135
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• 2006

최근 들어 자동화된 시맨틱 웹 서비스 조합을 위해 인공지능 계획 기법을 이용하려는 연구가 활발하다. 하지만 이러한 계획 기법이 효과적으로 적용되기 위해서는 먼저 시맨틱 웹 서비스의 명세와 온톨로지들을 계획기에서 이용 가능한 계획 영역 지식 형태로 변환하여야 한다. 본 논문에서는 OWL-S로 기술된 웹 서비스 명세와 OWL로 정의된 온톨로지를 표준 계획영역지식 표현언어인 PDDL로 변환하는 변환기의 설계와 구현에 대해 설명한다. 이 변환기의 특징은 기존의 OWLS2PDDL와는 달리 KIF 기반의 전제조건과 효과에 대한 변환 기능을 추가로 제공하며, 웹 서비스의 입출력 데이터에 대한 명세변환도 보다 실용적으로 간소화하였다. 또한, 이 변환기는 계획을 위한 영역모델과 이 영역모델에 기초한 다양한 문제모델들을 별도로 분리하여 생성하며, 이 두 모델 모두에 온톨로지가 적용될 수 있도록 허용한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.259-269
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• 2013

In this paper, we propose an SIW(Substrate Integrated Waveguide) multi-section E-plane transformer using air-holes for an SIW system with variable thicknesses. Air-holes are inserted into a SIW E-plane quarter wavelength transformer for matching an E-plane impedance discontinuity. A PSIW(Punched Substrate Integrated Waveguide) consisted of air-holes has an SIW characteristic impedance tunability because of reducing a equivalent shunt capacitance of the SIW. And, a PSIW multi-section E-plane transformer is implemented for improving a matching bandwidth by using the Chebyshev polynomial. The measurement results of PSIW double-section E-plane transformer show that the insertion loss($S_{21}$) is $1.57{\pm}0.11$ dB and input return loss($S_{11}$) is more than 15 dB from 11.45 GHz to 13.6 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1484-1491
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• 2020

Since the slot line transmits electric and magnetic signals through the slot, the size of the slot greatly affects the signal power loss. In order to have low loss, the slot line is mainly used at a high frequency of above 3GHz on a substrate having a high dielectric constant(er). This paper proposes the 4:1 impedance transformer using a slot line on TLC-30 laminate (h=20mil, er=3.0; Taconic) being a relatively low dielectric constant at a frequency of 1.85GHz. In the proposed impedance transformer, the dielectric resonator is arranged on the slot line to reduce signal loss occurring at the slot line. The proposed 4:1 microstrip-slot line impedance transformer fabricated using a (Zr,Sn)TiO4 dielectric resonator(er=38) has the transmission loss(S21) of -0.375dB and the reflection value(S11) of -27.6dB at 1.855GHz. This confirms that the slot line can be stably used even in a low dielectric constant substrate and a low frequency region by using a dielectric resonator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.