• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.4
• /
• pp.471-477
• /
• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• Proceedings of the Korean Geotechical Society Conference
• /
• 2008.10a
• /
• pp.1167-1174
• /
• 2008

Vertical drain method, which is one of the soft ground improvement methods, shorten s drain path to accelerate consolidation process and is applied in many sites. At a recent, composite discharge capacity experiment that analyze discharge amount by consolidation behavior with overburden pressure of soft ground in laboratory, simulates similarly with actuality. Geotechnical engineering problems such a s soft ground improvement are solved by numerical analysis by development of computer and numerical analysis techniques. Numerical analysis does that result is contrary by user's inexperience for choice of constitution model and application of analysis method. Therefore, this thesis experiments on composite discharge capacity test and study discharge capacity of drain and consolidation behavior of soft ground installed prefabricated vertical drain boards. Also, This thesis studied reasonable input parameters and constitution model by compare results of composite discharge capacity test and numerical analysis using PLAXIS that is 2D finial element numerical analysis program.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.2
• /
• pp.15-22
• /
• 2013

Low-Temperature-cofired ceramics (LTCC) antenna packages have been extensively researched and utilized in recent years due to its excellent electrical properties and ease of implementing dense package integration topologies. This paper introduces some of the key research and development activities using LTCC packaging solutions for 60 GHz antennas at Samsung Electronics [1]. The LTCC 60 GHz antenna element topology is presented and its measured results are illustrated. However, despite its excellent performance, the high cost issues incurred with LTCC at millimeter wave (mmWave) frequencies for antenna packages remains one of the key impediments to mass market commercialization of mmWave antennas. To address this matter, for the first time to the author's best knowledge this paper alleviates the high cost of mmWave antenna packaging by devising a novel, broadband antenna package that is wholly based on low-cost, high volume FR4 Printed Circuit Board (PCB). The electrical properties of the FR4 substrate are first characterized to examine its feasibility at 60 GHz. Afterwards a compact multi-layer antenna package which exhibits more than 9 GHz measured bandwidth ($S_{11}{\leq}-10$ dB) from 57~66 GHz is devised. The measured normalized far-field radiation patterns and radiation efficiency are also presented and discussed.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.26 no.4
• /
• pp.255-259
• /
• 2006

For the intruder detection, a buried fiber-optic sensor based on fiber-optic Mach-Zehnder interferometer is demonstrated. We buried the sensor arm in a styrene board and exerted pressure on it. The pressure-induced deformation speed has almost linear relationship with the output frequencies of the interference signals, and about 4.25 Hz frequency change per 0.01m/s was obtained. Also it has been shown that the amplitude of frequency component increases according to the weight of mass.

• Proceedings of the Korean Society For Composite Materials Conference
• /
• 2002.05a
• /
• pp.181-183
• /
• 2002

The accurate permeability for preform is critical to model and design the impregnation of fluid resin in the composite manufacturing process. In this study, the in-plane and transverse permeability for a woven fabric are predicted numerically through the coupled flow model which combines microscopic with macroscopic flow. The microscopic and macroscopic flow which are flows within the micro-unit and macro-unit cell, respectively, are calculated by using 3-D CVFEM(control volume finite element method). To avoid checker-board pressure field and improve the efficiency on numerical computation, A new interpolation function for velocity is proposed on the basis of analytic solutions. The permeability of plain woven fabric is measured through unidirectional flow experiment and compared with the permeability calculated numerically. Based on the good agreement of the results, the relationships between the permeability and the structures of preform such as the fiber volume fraction and stacking effect can be understood. The reverse and the simple stacking are taken in account. Unlike past literatures, this study is based on more realistic unit cell and the improved prediction of permeability can be achieved. It is observed that in-plane flow is more dominant than transverse flow in the real flow through preform and the stacking effect of multi-layered preform is negligible. Consequently, the proposed coupled flow model can be applied to modeling of real composite materials processing.

• International Journal of Automotive Technology
• /
• v.6 no.4
• /
• pp.333-340
• /
• 2005

In order to better quantify the contribution from nonroad sources to emission inventories, it is important to understand not only the emissions rates of these engines but also activity patterns that can be used to accurately portray their in-use operation. To date, however, very little information is available on the actual activity patterns of nonroad equipment. In this study, a total of 18 pieces of nonroad equipment were instrumented with collected data including intake manifold air pressure (MAP), exhaust temperature and, on a subset of vehicles, engine rpm and throttle position. The equipment included backhoes, compactors, dozers, motor graders, loaders and scrappers used in applications such as landfilling, street maintenance and general roadwork. The activity patterns varied considerably depending on the type of equipment and the application. Daily equipment operating time ranged from less than 30 minutes to more than 8 hours, with landfill equipment having the highest daily use. The number of engine starts per day ranged from 3-11 lover the fleet with an average of 5 starts per day. The average percent idle time for the fleet was approximately $25\%$ with a range from 11 to $65\%$ for individual pieces of equipment. Duty cycles based on exhaust temperature/throttle position profiles were also developed for two graders and one dozer.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.40 no.5
• /
• pp.332-346
• /
• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• Journal of Fashion Business
• /
• v.19 no.4
• /
• pp.153-167
• /
• 2015

This paper proposes knit slacks patterns by lower body shape of middle-aged women. In addition, this paper aims to propose a design method for a prototype of nice knit slacks using the properties of knitwear. To select basic woven slack patterns which would be used in designing prototype of knit slacks for middle-aged women, two industrial slack patterns and two educational slack patterns were collected, and lab coats were prefabricated using muslin. Then, a shape test was performed by an evaluation board which consisted of eight experts who majored in Clothing Construction. Using blended yarn (1/17's) with 64% wool, 23% rayon and 13% nylon, 12G knit slacks in plain stitch were made. In terms of waist circumference of knit slacks, the front and the back were set to W/4+1+2(D) and W/4-1+2(D), respectively, with 1cm of difference using waist circumference (Omphalion) to cover the abdominal circumference. To make the front-back width of the side line even, the front waist circumference was increased by 1cm. The ease of hip circumference was set to 4cm in total with H/4+1+0.8 in front and H/4+1-0.8 in the back (0.8cm in difference). Crotch length was set by adding 3cm (width of waist belt) after deducting crotch height from waist height (Omphalion). The center front angle was shifted by 1cm while the center back angle was shifted from the center front to the side line by 5cm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.2C
• /
• pp.291-297
• /
• 2004

In this paper, a new structure for the AEC(Acoustic Echo Canceller) is proposed in which echo signal components that can be created in mobile communications is effectively eliminated. Block Data Flow Architecture is a parallel architecture that achieves high performance, high efficiency, high throughput, and almost linear speed up. The proposed architecture employs AEC and is implemented using the TMS320C6711 for real-time applications. The proposed AEC shows improved performance by eliminating echoes at 55ms delay path. Since the proposed AEC can also be implemented in Firmware, it is believed to effectively work on various types of echoes if it is applied on CDMA mobile devices. The TMS320C6711 shows much better performance comparing to previous DSPs. For experimental verifications, filtering operation using adaptive algorithm is performed on TMS320C6711 board and error signals resulted from computations are monitored on PC, and then the performance of the implemented AEC is verified through ERLE computation. According the results of simulation, good characteristic of 100dB are shown after 500 sampling data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.4
• /
• pp.424-434
• /
• 2015

Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.