• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1672-1678
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• 2007

The communication systems and characteristics of transmit are very importance a serious view of ubiquitores society. The high rate systems have to construct for data of voice, graphics and moving-video with the multimedia to transmit on the low frequency band. The rate of data are relation that there are the bandwidth of line and channels, the bit per second and communication-systems. This paper study for the error performance of 2, 4 8 level FSK to transmit amount of data in the communication systems and design to FDM system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.3
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• pp.69-74
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• 2009

A novel protocol is proposed to achieve sub-carner-based rate adaptation in OFDM-based wireless systems. The protocol requires the addition of one OFDM symbol to the Clear-to-Send (CTS) packet defined in the IEEE 802.11 standard_ When receiving a Ready-To-Send (RTS) packet, the receiver determines the number of bits to be allocated in each sub-carrier through channel estimation. This decision is delivered to the sender using an additional OFDM symbol. That is, bit-allocation over sub-carriers is achieved using only one additional OFDM symbol. The protocol also provides an error recovery process to synchronize the bit-allocation information between the sender and receiver. The protocol enhances the channel efficiency in spite of the overhead of one additional OFDM symbol.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.9
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• pp.1382-1391
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• 2022

White-box cryptography can respond to white-box attacks that can access and modify memory by safely hiding keys in the lookup table. However, because the size of lookup tables is large and the speed of encryption is slow, it is difficult to apply them to devices that require real-time while having limited resources, such as IoT(Internet of Things) devices. In this work, we propose a scheme for collecting short-length plaintexts and processing them at once, utilizing the characteristics that white-box ciphers process encryption on a lookup table size basis. As a result of comparing the proposed method, assuming that the table sizes of the Chow and XiaoLai schemes were 720KB(Kilobytes) and 18,000KB, respectively, memory usage reduced by about 29.9% and 1.24% on average in the Chow and XiaoLai schemes. The latency was decreased by about 3.36% and about 2.6% on average in the Chow and XiaoLai schemes, respectively, at a Traffic Load Rate of 15 Mbps(Mega bit per second) or higher.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.183-187
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• 2000

In this paper, the performance of DS-CDMA system and FH-CDMA system has been comparision analyzed in a channel environment which is characterized by Multi-User environment and Rayleigh fading environment. The techniques of improvement of the performance has been comperision analysis evaluated when adopting MRC diversity techniques. In same condition, We are analyzed the BER(Bit Error Rate) as increase Use's number due to comparing performance of two systems by Same communication band(300KHz), jamming signal(JSR) 10∼20dB, user data-rate 300bps. In the result, the performance of DS and FH systems in multiuser and Rayleigh fading environment is improved performance when adopting MRC diversity techniques. Especially DS system has been improved performance about 9.5 times than FH system when adopting MRC diversity techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.817-825
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• 2013

The UHDTV system, which provides realistic service with ultra-high definite video and multi-channel audio, has been studied as a next generation broadcasting service. Since the conventional digital terrestrial transmission system is not capable to cover the increased transmission data rate of the UHDTV service, there are great necessity of researches about increase of data rate. Accordingly, the researches has been studied to increase the transmission data rate of the DVB-T2 system using dual-polarized MIMO technique and high order modulation. In order to optimize the MIMO DVB-T2 system where irregular LDPC codes are used, it is necessary to study the design of the bit mapper that matches the LDPC code and QAM symbols in MIMO channel. However, the research related to the design of the bit mapper has been limited to the SISO system. Therefore, this paper defines a new parameter that indicates the VND distribution of MIMO DVB-T2 system and performs the performance analysis according to the parameter which will be helpful for designing a MIMO bit mapper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2317-2325
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• 2016

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.

• Journal of Satellite, Information and Communications
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• v.9 no.3
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• pp.98-103
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• 2014

In this paper, we propose and analyze a novel interference cancellation scheme in cooperation communication environment in which a large number of users exist. In cooperative communication system consisting a source, destination, and relay, ad-hoc groups undergo a rapid degradation because of interference data form adjacent ad-hoc groups. To solve these problems, we propose Zero Forcing (FC) and Minimum Mean Square Error (MMSE) and make a dent in the magnitude of interference. Finally, we can obtain orignal data using Successive Interference Cancellation (SIC). The performance of proposed scheme is analyzed in terms of a bit error probability. The results of the paper can be applied to design of various ad-hoc networks for cooperation communication systems.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1053-1058
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• 2011

In this paper, we propose a concatenated single antenna diversity system to assure the data transmission reliability between flight type air nodes which move according to their atypical orbit, then analyze its performance. The proposed system achieve a diversity gain using single antenna and a coding gain from convolutional code simultaneously. Simulation result about the bit error rate(BER) of the proposed system shows that its BER performance is about 9.5dB greater than convolutional code at $10^{-4}$ and about 14dB greater than space time block code at $10^{-3}$ which has a full diversity gain. In addition, compared with space time trellis code with diversity gain and coding gain, the proposed system shows the better 4dB at a BER of $10^{-5}$. Therefore, it is necessary that concatenated single antenna diversity should be adopted to the reliable data transmission of flight type air nodes.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.