• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1241-1246
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• 2005

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glich-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in 0,35um Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification the prototype error between DNL and INL is less than ${\pm}0.09LSB$ respectively. Also, fab-out chip was tested, analysed the cause of error operation, and proposed the field considerations for chip test.

• 전자공학회논문지 IE
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• v.43 no.3
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• pp.6-12
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• 2006

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glitch-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in $0.35{\mu}m$ Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification and the prototype error between DNL and INL is less than $\pm$0.09LSB respectively. Also, the manufactured DAC chip was analyzed the cause of error operation and proposed the field considerations for chip test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.57-65
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• 2002

In this paper, a 2.5V 10-bit 300MSPS CMOS D/A Converter is described. The architecture of the D/A Converter is based on a current steering 8+2 segmented type, which reduces non-linearity error and other secondary effects. In order to achieve a high performance D/A Converter, a novel current cell with a low spurious deglitchnig circuit and a novel inverse thermomeer decoder are proposed. To verify the performance, it is integrated with $0.25{\mu}m$ CMOS 1-poly 5-metal technology. The effective chip area is $1.56mm^2$ and power consumption is about 84mW at 2.5V power supply. The simulation and experimental results show that the glitch energy is 0.9pVsec at fs=100MHz, 15pVsec at fs=300MHz in worst case, respectively. Further, both of INL and DNL are within ${\pm}$1.5LSB, and the SFDR is about 45dB when sampling, frequency, is 300MHz and output frequency is 1MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.