• Journal of the Institute of Convergence Signal Processing
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• v.5 no.1
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• pp.40-45
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• 2004

This paper presents the parallel distributed control scheme for shaping of the bent glass. The designed system consists of a PC, a main controller and 11 servo-controllers, the precision motion controllers. Each elements are connected by using RS-232C and 8-bit data bus. In order to guarantee the stability and the control performance, we use a precision PID motion controller and a H-bridge on the servo-drivers. PC calculates position values of 11 DC motors by using the pre-determined curvature value and offers the user interface environment operator. The main controller provides the control instructions and parameter values to 11 servo-controllers by chip enable signal, simultaneously. Using the received commands and parameter values, the servo-controllers control the positions of the DC motors based on PID control scheme.

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1229-1239
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• 1996

The increase of additional information broadcasting of TV demands a graphic overlay processor. This paper is about the design, implementation and testing of a graphic overlay processor called by KBPS decoder ASSP (Applicatio n Specific Standard Product) which is compliance with Korea Broadcast Programming System. KBPS decoder ASSP consists of embedded 8 bit microprocessor Z80, graphic overlay controller, KBPS schedule decoder, memory controller, priority interrupt controller, MIDI controller, infrared raccoon receiver, async scrial communication controller, timer, bus controller, universal parallel input-output port and serial-parallel interface. The 0.8 micron CMOS Sea of Gate is used to implement the ASSP in amount of about 31,500 gates, and it is running at 14.318MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.252-259
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• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• The KIPS Transactions:PartC
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• v.16C no.5
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• pp.583-588
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• 2009

Network intrusion detection system (NIDS) monitors all incoming packets in the network and detects packets that are malicious to internal system. The NIDS should also have ability to update detection rules because new attack patterns are unpredictable. Incorporating FPGAs into the NIDS is one of the best solutions that can provide both high performance and high flexibility comparing with other approaches such as software solutions. In this paper we propose and design a novel approach, prefix sharing parallel pattern matcher, that can not only minimize additional resources but also maximize the processing performance. Experimental results showed that the throughput for 16-bit input is twice larger than for 8-bit input but the used LEs/Char in FPGA increases only 1.07 times.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.