• Journal of Power Electronics
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• 제10권4호
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• pp.374-381
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• 2010

Typical power electronic converters employ only pulse width modulation (PWM) to generate specific switching patterns. In this paper, a novel control strategy combining both pulse-width and amplitude modulation strategies (PWAM) has been proposed for power converters. The Pulse Amplitude Modulation (PAM), used in communication systems, has been applied to power electronic converters. This increases the degrees of freedom in eliminating or mitigating harmonics when compared to the conventional PWM strategies. The role of PAM in the novel PWAM strategy is based on the control of the converter's dc sources values. Software implementation of the conventional PWM and the PWAM control strategies has been applied to a five-level inverter for mitigating selective harmonics. Results show the superiority of the proposed strategy from the THD point of view along with a reduction in the inverter power dissipation.

• 한국콘텐츠학회논문지
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• 제7권1호
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• pp.116-123
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• 2007

본 논문은 OLED 패널 소스 구동회로에서 구동 전류의 크기와 폭을 조절하는 새로운 amplitude width modulation(AWM) 방식을 제안하였다. 기존의 소스 구동회로에서 pulse amplitude modulation(PAM) 방식은 DAC 회로 추가로 인해 크기가 커진다는 단점이 있고, pulse width modulation(PWM) 방식은 낮은 그레이 신호 레벨에서 발광 효율이 나쁜 단점이 있다. 이와 같은 단점을 개선하기 위해 본 논문에는 색상 데이터 비트의 MSB를 이용하여 구동 전류의 레벨을 제어하고, 데이터 비트의 LSB를 이용하여 구동 전류의 폭을 조정하는 구동방식을 제안하였다. 제안된 구동 방식은 $0.35-{\mu}m$ 3-poly 4-metal CMOS high voltage 공정을 사용하여 구현하였다. 시뮬레이션 결과는 제안된 AWM 구동 회로가 PAM 방식에 비해 회로 크기를 줄였고 신호 레벨이 낮은 영역에서 PAM과 거의 동일한 발광 효율을 얻었다.

• 전력전자학회논문지
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• 제19권4호
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• pp.320-326
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• 2014

In this paper, the new smart dimming algorithm which is mixed with PWM and PAM control method is proposed for reducing the power consumption of LED TV Backlight. The proposed technique is using the curve characteristics of LED forward voltage and current which is proportionally changing LED forward voltage as changing LED forward current. Therefore, each PWM and PAM control method has different LED forward voltage and current in the same brightness condition. The PWM control method adjusts the brightness of LED TV Backlight by only varying the duty ratio of PWM and constantly sustaining the amplitude of LED forward current and voltage. So, the level of LED forward current and voltage in the PWM control method is relatively high and constant regardless of duty ratio of PWM. On the other hand, the PAM control method adjusts the brightness of LED TV Backlight by directly varying the level of LED forward current. So, the level of LED forward current and voltage in the PAM control method is lowered according to the brightness level. For the above-mentioned reason, the PAM control method has the advantage of reducing the total power consumption of LED TV Backlight at the brightness condition of below 100%, compared with PWM control method. By implementing this characteristic to LED driver circuit with control algorithm in MCU, the power consumption of LED TV Backlight can expect to be reduced. The effectiveness of the proposed method, new smart dimming algorithm, CPWAM(=Conditional Pulse Width Amplitude Modulation), has been verified by experimental results.

• 대한전자공학회논문지SD
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• 제46권11호
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• pp.84-91
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• 2009

본 논문은 multi-level signaling을 이용한 high speed serial link transmitter에 관하여 제안하였다. High speed serial link에서 수 Gb/s를 달성하기 위해 4-pulse amplitude modulation (PAM) 을 사용하였다. 4-PAM은 4개의 level로 한 symbol time에 2 bit data를 전송함으로써 binary signaling보다 2배 빠른 data 전송이 가능해졌다. 제안된 4-PAM transmitter는 전압 output 대신 전류 output을 생성하며 이로 인해 driver의 switching time이 빨라져서 더 높은 속도의 transmitter를 구현할 수 있었다. $2^5-1$ pseudo-random bit sequence (PRBS) 생성기는 built-in self test (BIST)를 하기 위해 on-chip으로 설계되었다. 본 연구는 동부 하이텍 $0.18{\mu}m$ CMOS 공정을 통하여 설계되었으며 1.8 V supply voltage에서 eye 크기가 160 mV 이고 최대 동작 속도는 8 Gb/s이다. 칩 전체 면적은 $0.7\times0.6mm^2$이며 전력 소모는 98 mW이다.

• 한국광학회지
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• 제34권4호
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• pp.151-156
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• 2023

파장당 200 Gb/s급 신호를 전송하는 고속 근거리 광통신 시스템을 비용 효율적으로 구축하기 위한 방안으로서 캐리어 억제 펄스 기반의 2채널 광학적 시분할 다중화 시스템을 제안한다. 캐리어 억제 펄스는 널 바이어스가 인가된 마하 젠더 변조기로 생성되며, 이는 시분할 다중화 신호를 색분산에 강인하게 만든다. 송신부에서는 캐리어 억제 펄스를 둘로 분기하고, 각각을 100 Gb/s의 4레벨 진폭 변조 신호로 변조한 후, 광학적 시분할 다중화를 통해 200 Gb/s의 신호를 생성한다. 다중화된 광 신호는 광섬유로 전송된 후, 반도체 광 증폭기로 증폭되며, 한 개의 광 검출기로 검출된다. 증폭기에 의해 발생한 잡음은 광학 필터로 제거된다. 시분할 다중화 과정에서 발생하는 누화는 다중 입력-다중 출력 이퀄라이저로 보상한다. 본 연구에서는 200 Gb/s의 고속 신호를 40 ps/nm의 색분산을 갖는 광섬유로 전송하여도 3.8×10^-3 이하의 비트 오율을 확보할 수 있음을 시뮬레이션으로 확인하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1749-1753
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• 2003

We proposed several systems for 1Giga bit Modem. The first, Binary ASK(Amplitude Shift Keying) system has a high speed shutter transmitter and no IF(Intermediate Frequency) receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation. The second, Binary phase modulation system has a high speed shutter transmitter and IF-VCO(IF-Voltage Controlled Oscillator) control by base-band phase rotation. Polarity of shutter window is changed by the binary data. The window should be narrow same as above ASK. The advantage of proposed system is which error rate performance is superior. The disadvantage of proposed system are that Circuitry is more complex, narrow pull-in range of receiver caused by VCO and spectrum divergence by the non-linear amplifier. The third, 4-QAM(Quadrature Amplitude Modulation)system has a nyquist pulse transmitter and IF-VCO control by symbol clock. The advantage of proposed system are that signal frequency band is a half of 1GHz, reliable pull-in of VCO and possibility of double speed transmission(2Gbps) by keeping 1GHz frequency-band. The disadvantage of proposed system are that circuit complexity of pulse shaping and spectrum divergence by the non-linear amplifier.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• ETRI Journal
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• 제43권5호
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• pp.923-931
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• 2021

We studied the influence of GaAs top-layer thickness on the small-signal modulation response and 56 Gb/s four-level pulse-amplitude modulation eye quality of 850 nm vertical-cavity surface-emitting lasers (VCSELs). We considered the proportionality of the gain-saturation coefficient to the photon lifetime. The simulation results that employed the transfer-matrix method and laser rate equations led to the conclusion that the proportionality should be considered for proper explanation of the experimental results. From the obtained optical eyes, we could determine an optimum thickness of the GaAs top layer that rendered the best eye quality of VCSEL. We also compared two results: one result with a fixed gain-saturation coefficient and the other that considered the proportionality. The former result with the constant gain-saturation coefficient demonstrated a better eye quality and a wider optimum range of the GaAs top-layer thickness because the resultant higher damping reduced the relaxation oscillation.

• ETRI Journal
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• 제37권6호
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• pp.1120-1128
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• 2015

We propose a pseudo optical N-level pulse-amplitude modulation (PO PAM-N) signal using a few externally-modulated lasers (EMLs) operating at different wavelengths, which is suitable for upgrading the transmission speed over an optical link of < 10 km single-mode fiber with low-cost components. To compare a PO PAM-N signal with that of a standard optical PAM-N signal, we perform experiments for evaluating the performance of a 51.56-Gb/s PO PAM-4 signal and standard 51.56-Gb/s optical PAM-4 signal. The receiver sensitivity (at $BER=10^{-5}$) of the PO PAM-4 signal is 1.5 dB better than the receiver sensitivity of a standard optical PAM-4 signal. We also investigate the feasibility of PO PAM-N (N = 4, 8, and 16) signals operating at 103.12 Gb/s, considering relative intensity noise, timing jitter, extinction ratio (ER) of EMLs, and dispersion. From the results, a PO PAM-8 signal performs better than PO PAM-4 and PO PAM-16 signals at 103.12 Gb/s. Finally, we suggest a timing control method to suppress the effect of dispersion in a PO PAM-N signal. We show that the tolerance to dispersion of a 103.12-Gb/s PO PAM-8 signal can be improved to ${\pm}40ps/nm$ by applying a proposed scheme.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.