• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.99-105
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• 2004

A shared-capacitor charge-sharing ROM (SCCS-ROM) using dummy bit lines is proposed. The SCCS-ROM reduces the bit line swing voltage using the charge-sharing technique of the conventional charge-sharing ROM (CS-ROM). Although the CS-ROM needs three small capacitors per output bit, the proposed SCCS-ROM shares the capacitors so that it needs only three capacitors. The SCCS-ROM implements the capacitors using dummy bit lines. This not only increases noise immunity but also reduces power. A SCCS-ROM with 8K${\times}$15bits implemented in a 0.35${\mu}{\textrm}{m}$ CMOS process. The SCCS-ROM consumes 8.63㎽ at 100MHz with 3.3V The simulation results show that the SCCS-ROM reduces 8.4% power compared to the CS-ROM.

• Analytical Science and Technology
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• v.5 no.3
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• pp.295-301
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• 1992

A versatile data acquisition and control adaptor for IBM personal computers has been developed. The data acquisition and control adaptor developed contains major components necessary for computerized data acquisition and control instrumentaions. Up to 4 differential analog signals can be acquired through a choice of dual 12-bit analog-to digital converters depending on the experimental requirements. Also, dual 12-bit digital-to-analog converters, three 16-bit programmable most computerized laboratory data acquisition and control instrumentation. The design principle and its applications are described.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.585-592
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• 2014

In this paper, we study the LEA[1] block cipher system in UICC-16bit only. Also, we explain a key-schedule function and encryption/decryption structures, propose an advanced modified key-scheduling, and perform LEA in UICC-16bit that we proposed advanced modified key-scheduling. Also, we compare LEA with ARIA that proposed domestic standard block cipher, and we evaluate the efficiency on the LEA algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.129-137
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• 2007

MPEG-4 FGS is one of scalable video coding schemes specified In ISO/IEC 14496-2 Amendment 2, and particularly standardized as a scheme for providing fine granular quality and temporal scalabilities. In this paper, we propose a sign-bit reduction technique in embedded bit-plane coding to enhance the coding efficiency of MPEG-4 FGS system. The general structure of the FGS system for the proposed scheme is based on the standard MPEG-4 FGS system. The proposed FGS enhancement-layer encoder takes as input the difference between the original DCT coefficient and the decision level of the quantizer instead of the difference between the original DCT coefficient and its reconstruction level. By this approach, the sign information of the enhancement-layer DCT coefficients can be the same as that of the base-layer ones at the same frequency index in DCT domain. Thus, overhead bits required for coding a lot of sign information of the enhancement-layer DCT coefficients in embedded bit-plane coding can be removed from the generated bitstream. It is shown by simulations that the proposed FGS coding system provides better coding performance, compared to the MPEG-4 FGS system in terms of compression efficiency.

• Journal of Broadcast Engineering
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• v.14 no.1
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• pp.70-80
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• 2009

We propose an ideal line coding for high speed data communication in visible light communication system. B4-HBT line coding is defined as follow. The 1 bit is +V at first though 1 encodes +Voltage and -Voltage doing change of shift each other, then -V newly. V that is been mutually contradictory for 1 bit that exist before that if continuous 0 bits exist 4 here same and reduces mistake because has reverse mark V in 4 continuous last 0 bits and gives half bit variation in 1 bit and made effect of noise low. 2${\sim}$3 dB profit is seen comparing with line coding that exist in simulation result.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.3 s.234
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• pp.418-424
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• 2005

We present the design, fabrication and experimental results of 4-bit digital microinjectors, whose ejected droplet volumes are adjusted by the digital operation of a 4-bit microheater array. We design the reference microinjectors as well as its comparative test structures. In the fabrication process, we use a five-mask micromachining process and the total chip size of the fabricated microinjector is $7,640{\mu}m{\times}5,260{\mu}m.$ We measure the ejected droplet volumes and velocities, which are adjusted from $12.1{\pm}1.0~55.6{\pm}14.7pl\;and\;2.3{\pm}0.1~15.7{\pm}0.8m/s.$ respectively, depending on the 15 possible combinations of 4-bit microheater array. We also experimentally characterize the effect of geometric variation including the microheater size, inter-microheater gap, microchannel width and sequential operation of microheater array on the ejected droplet volume and velocity. Among these parameters, we find that the microheater size is the most dominant parameter affected to the ejected droplet volumes and velocities. Thus, the present microinjector has a potential for application to the high-resolution inkjet printers with multiple gray levels or high-precision fluid injectors with variable volume control.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.297-310
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• 2013

In this paper, we present a model-based video bit rate estimation scheme for reducing the bit rate while maintaining a subjective quality in many video streaming services limited by network bandwidth, such as IPTV services. First, we extract major parameters which serve as an indirect measurement of frame's bits. Using those parameters, the proposed bit rate estimation scheme can extract candidate frames. Finally, the bit rate of each segment is estimated by statistical analysis and a mathematical model based on a given target quality. In experimental results, we show that the proposed scheme can reduce the bit rate on average by 43% in low-complexity video while maintaining the subjective quality. To find the appropriate bit rate based on video contents, the proposed schemes can estimate the bit rate with neither the repeated full encoding nor subjective quality test. On average, the bit rate can be automatically estimated by encoding the candidate frames of 4%.