• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.6
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• pp.409-413
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• 2012

In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.

• Journal of the Korea Society of Computer and Information
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• v.9 no.3
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• pp.127-133
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• 2004

This study was carried out develope a temperature control system of temperature control by used K-thermocouple. This system was producted a stable voltage regulator 22Bit of digital converter and 22Bit of resolution. It was producted a micro voltage of 25 times amplification and controlled a DC0.1V~DC4.7V within 0～120$0^{\circ}C$. We designed block-diagram of hardware and software by PIC16C74 in a micro-controller, we are made up of a VFD function and can be used interface of a power block.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.26-35
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• 1997

This paper proposes a multi-bit $\Sigma\Delta$ modulator arcitecture which eliminates signal clipping problem. To avoid signal clipping, the output values of intgrators are monitored and modified by a reference value. This oepration is recorded as a digital code to restore actual signal value. Due to the digital code, the substraction of feedback value from the multi-bit quantizer can be calculated by a digital adder and this simplifies dAC operation making the accurate DAC of conventional multi-bit $\Sigma\Delta$ modulator scheme unnecessary. These features make N-th modulator can be implemented by sharing an integrator among N stages to decrease the required chip area. As an experimental example, a 4th order .sum..DELTA. modulator with oversampling ratio of 64 was simulated to show over 130 DB SNR at rail-to-rail input sinusoidal signal.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.591-595
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• 2011

In this paper, we design the hardware architecture of the BICM(Bit Interleaved Coded Modulation) module for next generation European broadcast system and implement the BICM module with DSP(Digital Signal Processor) TMS320C6474. Simulation result shows that the BER(Bit Error Rate) performance of the fixed-point BICM module using more than 8 bits is very similar to that of the floating-point BICM module.

• Proceedings of the KAIS Fall Conference
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• 2008.11a
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• pp.219-222
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• 2008

본 논문에서는 WDM시스템에서 사용될 수 있는 광전치증폭기의 수신감도를 해석하였다. $10^{-9}$의 에러확률에 대하여 FSK전송을 이용하여 비트당 광자수를 계산하여다. 결과로 일반적인 PIN 수신기의 수신감도는 $9.2{\times}10^4$ photon/bit이고, 광전치증폭수신기의 경우는 $7{\times}10^2$의 phton/bit를 갖음을 확인하였다. 또한 FSK전송의 경우에는 표준에러확률인 $10^{-9}$을 유지하기 위해 필요로 하는 비트당 광자의 수를 계산하였는데, 가우시안 근사해석법을 사용한 경우와 정확한 해석법(k자승법)을 이용한 결과 m=30인 경우 k자승법의 경우는 $2.36{\times}10^2$ photon/bit, 가우시안 근사법의 경우에는 $4.01{\times}10^2$ photon/bit을 얻었다. 이를 통해 동일한 BER의 경우에 광전치증폭수신기가 PIN수신기에 비해 우수함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1167-1176
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• 2004

This paper presents an adaptive MC-CDMA transmission for downlink in mobile satellite system and simulation results on Ka-band mobile satellite channel. The simulation results show that the proposed scheme support a throughput of several tens of Mbit/s and a spectral efficiency range of 1 bit/s/Hz to 4.7 bit/s/Hz according to channel environments due to the adaptive broadband satellite transmission.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.24-29
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• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.1-8
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• 2009

This paper proposes a 24-bit floating point multiply and accumulate(MAC) unit that can be used in geometry transformation process in 3D graphics. The MAC unit is composed of floating point multiplier and floating point accumulator. When separate multiplier and accumulator are used, matrix calculation, used in the transformation process, can't use continuous accumulation values. In the proposed MAC unit the accumulator can get continuous input from the multiplier and the calculation time is reduced. The MAC unit uses about 4,300 gates and can be operated at 150 MHz frequency.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.