• 한국전자파학회논문지
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• 제18권8호
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• pp.873-879
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• 2007

본 논문에서는 Freescale사의 Si-LDMOSFET 4-W 소자를 이용하여 고효율 class-F 전력 증폭기를 구현하였다. Class-F 전력 증폭기를 구현하는데 있어서 모든 하모닉 성분들에 대해 원하는 임피던스를 갖도록 조정하기는 불가능하기 때문에 2차와3차 하모닉 성분만을 조율하여 회로의 간결함과 동시에 상대적으로 높은 효율을 얻을 수 있었다. 또한, 본 논문에 설계된 증폭기는 보다 정확하게 하모닉 성분을 조율하기 위해, LDMOSFET의 대신 호 등가 모델에서 가장 큰 영향을 미치는 drain-source capacitance(Cds)와 bonding inductance(Lb)를 추출하여 하모닉 조율 회로를 설계하였다 제작된 고효율 class-F 전력 증폭기의 측정 결과 drain-efficiency(DE) 65.1%, power-added-efficiency(PAE) 60.3%의 효율을 얻을 수 있었다.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Carbon letters
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• 제21권
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• pp.68-73
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• 2017

We have demonstrated the production of thin films containing multilayer graphene-coated copper nanoparticles (MGCNs) by a commercial electrodeposition method. The MGCNs were produced by electrical wire explosion, an easily applied technique for creating hybrid metal nanoparticles. The nanoparticles had average diameters of 10-120 nm and quasi-spherical morphologies. We made a complex-electrodeposited copper thin film (CETF) with a thickness of $4.8{\mu}m$ by adding 300 ppm MGCNs to the electrolyte solution and performing electrodeposition. We measured the electric properties and performed corrosion testing of the CETF. Raman spectroscopy was used to measure the bonding characteristics and estimate the number of layers in the graphene films. The resistivity of the bare-electrodeposited copper thin film (BETF) was $2.092{\times}10^{-6}{\Omega}{\cdot}cm$, and the resistivity of the CETF after the addition of 300 ppm MGCNs was decreased by 2% to ${\sim}2.049{\times}10^{-6}{\Omega}{\cdot}cm$. The corrosion resistance of the BETF was $9.306{\Omega}$, while that of the CETF was increased to 20.04 Ω. Therefore, the CETF with MGCNs can be used in interconnection circuits for printed circuit boards or semiconductor devices on the basis of its low resistivity and high corrosion resistance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.524-533
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• 2017

This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a $180-{\mu}m$ CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.

• Journal of electromagnetic engineering and science
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• 제9권1호
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• pp.25-31
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• 2009

This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSMIEDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30$\sim$50 MHz/V) and an on-chip $2^{nd}$ harmonic noise filter. The proposed VCO is implemented in $0.13{\mu}m$ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of -123 dBc/Hz at 400 kHz offset and -145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is -183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies $0.45{\times}0.9\;mm^2$.

• Journal of Magnetics
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• 제15권4호
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• pp.194-198
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• 2010

In our present work, we developed a GMI (giant magnetoimpedance) sensor system to detect magnetic fields in the milli gauss range based on the asymmetric magnetoimpedance (AGMI) effect in Co-based amorphous ribbon with self bias field produced by field-annealing in open air. The system comprises magnetoimpedance sensor probe, signal conditioning circuits, A/D converter, USB controller, notebook computer, and program for measurement and display. Sensor probe was constructed by wire-bonding the cobalt based amorphous ribbon with dimensions $10\;mm\;{\times}\;1\;mm\;{\times}\;20\;{\mu}m$ on a printed circuit board. Negative feedback was used to remove the hysteresis and temperature dependence and to increase the linearity of the system. Sensitivity of the milli gauss meter was 0.3 V/Oe and the magnetic field resolution and environmental noise level were less than 0.01 Oe and 2 mOe, respectively, in an unshielded room.

• 대한전자공학회논문지
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• 제9권5호
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• pp.27-33
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• 1972

This paper describes the computer-aided design, fabrication and performance of high Q and high gain active filters suitable for microminiaturization in the frequency range of 10-800MHz, based on the negative resistance operation of a transistor. 48 as high as 1000 and a transducer gain as high as 35dB can readily be obtained with a single-transistor amplifier and with an inductance as small as a few nH at higher frequencies and 150 nH at lower frequencies in tile above frequency range. The gain of the proposed active filter can be stoabilized within $\pm$ 1.5 dB over the temperature range -1$0^{\circ}C$ to +5$0^{\circ}C$ and the temperature dependence of the center frequency is tapicalla 50ppm/$^{\circ}C$. An experimental FM receiver utilizing these fitters and operating at a carrier frequency of 92 MH3 was built. The whole circuit was fabricated on eight alumina substrates of by the thick-film hybrid IC technique and the coils are constructed, for miniaturization, in a spiral form of 3 or 4 turns of enamel copper wire with an overall diameter of about 5mm. The test results are also reported in this paper.

• 센서학회지
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• 제4권4호
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• pp.29-40
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• 1995

본논문(本論文)에서는 정전유도(靜電誘導) 트랜지스터의 잡음원인분석(雜音原因分析)을 위하여 직류(直流) 및 잡음특성(雜音特性), 잔존성분(殘存成分), 입력용량등(入力容量等)의 정무화(定武化)에 필요(必要)한 잡음(雜音) 등가회로(等價回路)를 제안(提案)하였다. 가장 단순(單純)한 잡음(雜音) 등가회로(等價回路)는 정전유도(靜電誘導) 트랜지스터의 동작원리(動作原理)에 의한 모델이며, 이 모델에 의한 실측치(實測値)가 산탄(shot) 잡음(雜音)보다 작게 나타났다. 소스 저항(抵抗)이 삽입(揷入)된 등가회로(等價回路)에서는 소스 저항(抵抗)의 부귀환효과(負歸還效果)에 의하여 산탄 잡음(雜音)이 저감(低減)됨을 확인(確認)하였다. 정확(正確)한 잡음저감원인(雜音低減原因)을 분석(分析)하기 위하여 소스 저항(抵抗)과 드레인 저항(低抗)의 계산식(計算式)을 유도(誘導)하기 위한 등가회로(等價回路)를 제안(提案)하였다. 등가회로(等價回路) 확인(確認) 실험(實驗)에서는 잔존성분(殘存成分)에 대한 신호원저항(信號源抵抗)과 출력부하저항(出力負荷抵抗)의 영향(影響)은 작으며, 잔존성분(殘存成分)은 입력환산등가잡음저항(入力換算等價雜音抵抗)으로 나타낼 수 있다. 또한, 입력용량(入力容量)은 부하저항(負荷抵抗)이 $0{\Omega}$일 때 13.6pF이며, 게이트 배선등(配線等) 정전유도(靜電誘導) 트랜지스터 동작(動作)에 직접(直接) 관여(關與)하지 않는 용량(容量)은 10pF정도(程度)이다.

• 전기전자학회논문지
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• 제18권4호
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• pp.559-565
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• 2014

가장 많이 쓰이는 FR4 이층 기판을 사용하여 3 dB 커플러를 설계하고 제작하였다. 커플러 일부의 겹치는 면적을 키워서 커플링을 증가시키고 대역폭을 증가시키는 구조를 제안하였다. 설계를 위한 주요 파라미터 값들을 여러 조건에 따라 도시하였고, 시뮬레이션과 측정을 통해 검증하였다. 제작된 커플러의 크기는 $30{\times}14mm^2$이고, 중심 주파수 2.5 GHz 에서 0.6 dB의 삽입 손실과 $90.5^{\circ}$의 위상차를 측정으로부터 얻었다. 측정된 삽입 손실 $3.6{\pm}0.5dB$에 대한 주파수 범위는 1.72 GHz에서 3.08 GHz이다. 제안한 커플러는 기존의 랭 커플러와 유사한 성능을 보였고, 와이어 본딩 공정이 필요 없어 추가 비용이 들지 않고 도선의 폭과 간격이 넓어서 제작이 용이하다.

• 한국전자파학회논문지
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• 제17권2호
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• pp.134-138
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• 2006

S-대역 SPST MMIC 스위치의 격리도 특성을 두 서로 다른 RF 결합 방법 인 마이크로스트립(microstirp)과 접지 코플라나 웨이브가이드(GCPW) 선로로 구성하여 분석하였다. 스위치의 온-오프 격리도는 마이크로스트립 설계에 비하여 접지 코플라나 웨이브가이드 선로를 사용하는 경우 5.8 dB 개선되었고, 접지 코플라나 웨이브가이드 선로에 코플라나 와이어본드 결합을 적용하는 경우 6.9 dB 더 향상된 격리도 특성을 3.4 GHz의 주파수에서 얻을 수 있었다. 측정된 삽입 손실 및 IMD3는 $3.2{\sim}3.6\;GHz$ 대역에서 1.94 dB보다 작았으며, 64 dBc보다 큰 특성을 얻었다.