• Title/Summary/Keyword: 3D packaging materials

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Implementation of Front End Module for 2.4GHz WLAN Band (2.4GHz 무선랜 대역을 위한 Front End Module 구현)

  • Lee, Yun-Sang;Ryu, Jong-In;Kim, Dong-Su;Kim, Jun-Chul;Park, Jong-Dae;Kang, Nam-Kee
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.1
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    • pp.19-25
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    • 2008
  • In this paper, the front end module (FEM) was proposed for 2.4GHz WLAN band by LTCC multilayer application. The FEM was composed of power amplifier IC, switch IC, and LTCC module. LTCC module consists of output matching circuit and lowpass filter as Tx part, bandpass filter as Rx part. Design of output matching circuit for LTCC was used matching parameter from output matching circuit based on lumped circuit on the PCB board. The dielectric constant of LTCC substrate is 9. The substrate was composed of total 26 layers with each 30um thickness. Ag paste was used for the internal pattern as the conductor material. The size of the module is $4.5mm{\times}3.2mm{\times}1.4mm$. The fabricated FEM showed the gain of 21dB, ACPR of less than -31dBc first side lobe and Less than -59dBc second side lobe and the output power of 23Bm at P1dB.

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Development of High-Quality LTCC Solenoid Inductor using Solder ball and Air Cavity for 3-D SiP

  • Bae, Hyun-Cheol;Choi, Kwang-Seong;Eom, Yong-Sung;Kim, Sung-Chan;Lee, Jong-Hyun;Moon, Jong-Tae
    • Journal of the Microelectronics and Packaging Society
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    • v.16 no.4
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    • pp.5-8
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    • 2009
  • In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

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3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Vacuum Packaging and Operating Properties of Micro-Tunneling Sensors

  • Park, H.W.;Lee, D.J.;Son, Y. B.;Park, J.H.;Oh, M. H.;Ju, B. K.
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.04a
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    • pp.110-110
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    • 2000
  • Cantilever-shaped lateral field emitters were fabricated and their electrical characteristics were tested. As shown in Fig.1, poly-silicon cantilevers were fabricated by the surface micromachining and they were used to the vacuum magnetic field sensors. The tunneling devices were vacuum sealed with the tubeless packaging method, as shown in Fig.2 and Fig.3. The soda-lime glasses were used for better encapsulation, so the sputtered silicon and the glass layers on the soda-lime glasses were bonded together at 1x10$^{-6}$ Torr. The getter was activated after the vacuum sealing fur the stable emissions. The devices were tested outside of the vacuum chamber. Through vacuum packaging, the tunneling sensors can be utilized. Fig.4 shows that the sensor operates with the switching of the magnetic field. When the magnetic field was applied to the device, the anode currents were varied by the Lorentz force. The difference of anode currents can be varied with the strength of the applied magnetic field.

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Ultimate Heterogeneous Integration Technology for Super-Chip (슈퍼 칩 구현을 위한 헤테로집적화 기술)

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.4
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    • pp.1-9
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    • 2010
  • Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

The Effect of Electroplating Parameters on the Compositions and Morphologies of Sn-Ag Bumps (Sn-Ag 범프의 조성과 표면 형상에 영향을 미치는 도금 인자들에 관한 연구)

  • Kim, Jong-Yeon;Yoo, Jin;Bae, Jin-Soo;Lee, Jae-Ho
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.4
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    • pp.73-79
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    • 2003
  • With the variation of Ag concentration in bath, current density, duty cycle, additive and agitation for electroplating of Sn-Ag solder, the compositions and the morphologies of solder were studied. It was possible to controll Ag content in Sn-Ag solder by varying Ag concentration in bath and current density. The microstructure size of Sn-Ag solder decreased with increasing current density. Duty cycle of pulse electroplating and quantity of additive affected on Ag content of deposit and surface roughness. In this work eutectic Sn-Ag solder bumps with fine pitch of 30 $\mu\textrm{m}$ and height of 15 $\mu\textrm{m}$ was formed successfully. The Ag content of electrodeposited solder was confirmed by EDS and WDS analyses and the surface morphologies was analyzed by SEM and 3D surface analyzer.

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Expectation of Nanotechnology Applications in Packaging (나노기술 적용을 통한 포장 분야의 전망)

  • Kim, Jai-Neung;Lee, Youn-Suk
    • KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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    • v.12 no.1
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    • pp.27-34
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    • 2006
  • Nanotechnology is playing an increasingly important role in the development on most areas of science and technology. Because of its potential of providing novel performance at the nanoscale, the nanotechnology can influence a wide range of applications such as information, energy, environment and biology, all essential for socioeconomic development in the near future. In the packaging industry, the main applications of nanotechnology are (1) to enhance durability, (2) improve gas and oxygen barriers of raw materials for films and packaging, (3) create new functional sensors, and (4) lengthen shelf life for the packaged food quality and will also help in pharmaceuticals and cosmetics. Nanotechnology is growing in an international interactions which accelerate in science, education, and industrial R&D. Government, industries and the business sector in Korea have shown a strong ambition towards the development of nanotechnology for the future. Meanwhile, a strategic investment in packaging area is much smaller compared to supporting research and development (R&D) of various major research areas. This article were reviewed the status and trends of current packaging research and development activities using nanotechnology in Korea, USA, Japan, and other international nations.

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The Fabrication and Characterization of Embedded Switch Chip in Board for WiFi Application (WiFi용 스위치 칩 내장형 기판 기술에 관한 연구)

  • Park, Se-Hoon;Ryu, Jong-In;Kim, Jun-Chul;Youn, Je-Hyun;Kang, Nam-Kee;Park, Jong-Chul
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.3
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    • pp.53-58
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    • 2008
  • In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

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Warpage Simulation by the CTE mismatch in Blanket Structured Wafer Level 3D packaging

  • Kim, Seong Keol;Jang, Chong-Min;Hwang, Jung-Min;Park, Man-Chul
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.22 no.1
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    • pp.168-172
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    • 2013
  • In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

A Study on the Surface Patterns and Bonding Characteristics of Exposed Materials based on Wheel Grit Size during Package Grinding (패키지 연삭 시 휠 입도에 따른 노출된 가공물의 표면 양상과 접합 특성 연구)

  • Jin Park;Seojun Bae;Kwangil Kim;Jinho Lee;Sanggyu Jang;Yong-Nam Koh
    • Journal of the Microelectronics and Packaging Society
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    • v.31 no.3
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    • pp.72-79
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    • 2024
  • To realize high speed and high bandwidth in the 2.xD package structure, methods requiring high technology are being studied for processes such as interposer or bridge die bonding, as well as heterogeneous chip bonding. Particularly, the grinding process of bonding surfaces is considered a key technology. The method of bonding an interposer or bridge die including Cu layers to a substrate and then exposing metallic materials such as Cu, which can be electrically connected, through a grinding process to connect heterogeneous chips is an approach that utilizes conventional packaging techniques. However, to meet the yield and quality standards required for mass production in processes involving the large-scale bonding of micro-bumps, as seen in 2.xD packages, it is essential to develop techniques based on high precision. This paper investigates the multi-material grinding process for heterogeneous chip bonding in a 2.xD package structure, using the grit size of the grinding wheel as a variable. The study examines the surface patterns and bonding characteristics of the exposed materials achieved through the grinding process. Through this study, we aim to optimize the grinding process for high-quality bonding, thereby contributing to the development of advanced packaging technologies.