• 제목/요약/키워드: 3D offset method

검색결과 103건 처리시간 0.023초

곡선 절개형 바지의 패턴사이즈 변형방법과 가상착의곡면3D (Methods to determine the size of pant patterns with curved design lines and their three dimensional construction using 3D virtual fitting)

  • 이희란
    • 패션비즈니스
    • /
    • 제20권4호
    • /
    • pp.153-171
    • /
    • 2016
  • With the advent of smart clothing for health care and sports, the sophisticated designs with curved seams are drawing attention. One of the problems in those clothing is to determine the design curves in 2D pattern, such that it corresponds to the lines on the intended 3D body. Moreover, the difficulty increases when the original pattern needs to be changed for various sizes and body types. We compare two methods of pattern enlargement in this paper: one is the offset/projection type, and the other is the split grading type. For the enlarged pattern with offset/projection type, the 3D surface offset was first adopted to transform the standard lower body to the target larger size; next, the design lines were projected to the new 3D surface, following which the 3D pattern was developed from the newly transformed 3D surface. In the second method, the enlarged pant patterns were developed by the split grading method. Here, a 3D pattern was developed from the initial body, and then enlarged to the target size by the conventional split grading method. Two feminine pants patterns were examined by 3D virtual fitting. We observed that the 3D offset/projection pants pattern was well fitted, having an evenly distributed surplus, as compared with the sample developed using the split grading method. The difference between the two patterns were apparent at the location where several curved lines merged.

Shell Template Offset 도면을 활용한 선체 곡판 형상 복원 방법에 관한 연구 (A Study on the Method for Reconstructing the Shell Plates Surface from Shell Template Offset Drawing)

  • 황인혁;손승혁
    • 대한조선학회논문집
    • /
    • 제56권1호
    • /
    • pp.66-74
    • /
    • 2019
  • In the field of shipbuilding design, the use of 3D CAD is becoming commonplace, and most of the large shipyards are conducting 3D design. However at the production site, workers are still working on 2D drawings rather than 3D models. This tendency is even worse in small-scale shipyards and block manufacturing shops. Particularly, in a manufacturing shop that is engaged in the outsourcing of blocks, it may not be possible to provide 3D model. However, the demand for 3D models in the production field is steadily increasing. Therefore, it would be helpful if 3D model could be generated from a 2D drawing. In this paper, we propose a method to extract template and unfolded surface shape information from shell template offset drawing using computer vision technology. Also a 3D surface model was reconstructed and visualized from the extracted information. The result of this study is thought to be helpful in the work environment where 3D model information can not be obtained.

3차원 측정자료부터 자유곡면의 가공을 위한 공구경로생성 (Generating Cartesian Tool Paths for Machining Sculptured Surfaces from 3D Measurement Data)

  • 고병철;김광수
    • 대한산업공학회지
    • /
    • 제19권3호
    • /
    • pp.123-137
    • /
    • 1993
  • In this paper, an integrated approach is proposed to generate gouging-free Cartesian tool paths for machining sculptured surfaces from 3D measurement data. The integrated CAD/CAM system consists of two modules : offset surface module an Carteian tool path module. The offset surface module generates an offset surface of an object from its 3D measurement data, using an offsetting method and a surface fitting method. The offsetting is based on the idea that the envelope of an inversed tool generates an offset surface without self-intersection as the center of the inversed tool moves along on the surface of an object. The surface-fitting is the process of constructing a compact representation to model the surface of an object based on a fairly large number of data points. The resulting offset surtace is a composite Bezier surface without self-intersection. When an appropriate tool-approach direction is selected, the tool path module generates the Cartesian tool paths while the deviation of the tool paths from the surface stays within the user-specified tolerance. The tool path module is a two-step process. The first step adaptively subdivides the offset surface into subpatches until the thickness of each subpatch is small enough to satisfy the user-defined tolerance. The second step generates the Cartesian tool paths by calculating the intersection of the slicing planes and the adaptively subdivided subpatches. This tool path generation approach generates the gouging-free Cartesian CL tool paths, and optimizes the cutter movements by minimizing the number of interpolated points.

  • PDF

OFDM 시스템에서 주파수 오프셋 보정에 의한 CIR 성능 향상 (CIR Performance Enhancement by Frequency Offset Estimation in OFDM System)

  • 고성희;최정훈;이동호;김남
    • 한국통신학회논문지
    • /
    • 제34권4C호
    • /
    • pp.446-452
    • /
    • 2009
  • OFDM 시스템은 전송단자 수신단의 오실레이터의 불일치로 인해 발생하는 주파수 오프셋의 영향에 민감하다는 단점이 있다. 또한 주파수 오프셋은 ICI(Inter Carrier Interference) 문제를 발생시키고 부반송파 사이에 직교성을 왜곡한다. 본 논문에서는 ICI 영향을 분석하고, 기존의 SC 기법을 응용하여 새로운 알고리즘을 제안한다. 제안된 기법의 BER(Bit Error Rate)과 신호 품질을 결정짓는 CR(Carrier to Interference Ratio)을 분석하기 위하여 MATLAB 프로그램을 사용한다. 모의실험 결과, 주파수 오프셋이 0.3과 0.5 일 때 $10^{-3}$의 BER에서 BPSK 변조는 0.5dB, 1dB 이상, QPSK 변조는 1.6dB, 1.5dB 이상의 SNR 성능 향상을 보이며, CIR 성능도 최대 15dB 이상 향상 되었다. 결과적으로 제안한 기법이 기존의 기법보다 시스템 성능 향상에 효과적이다.

하우스킵핑 A/D 변환기의 테스트 알고리즘과 측정 (Test Algorithm and Measurement of Housekeeping A/D Converter)

  • 박용수;유흥균
    • 반도체디스플레이기술학회지
    • /
    • 제3권4호
    • /
    • pp.19-27
    • /
    • 2004
  • The characteristic evaluation of A/D converter is to measure the linearity of the converter. The evaluation of the linearity is to measure the DNL, INL, gain error and offset error in the various test parameters of A/D converter. Generally, DNL and INL are to be measured by the Histogram Test Algorithm in the DSP-based ATE environment. And gain error and offset error are to be measured by the calculation equation of the measuring algorithm. It is to propose the new Concurrent Histogram Test Algorithm for the test of the housekeeping A/D converter used in the CDMA cellular phone. Using the proposed method, it is to measure the DNL, INL, gain error and offset error concurrently and to show the measured results.

  • PDF

쾌속조형의 속도를 향상시키기 위한 알고리즘 (An Algorithm to Speed Up the Rapid Prototyping)

  • 고민석;장민호;왕지남;박상철
    • 한국정밀공학회지
    • /
    • 제25권3호
    • /
    • pp.157-164
    • /
    • 2008
  • While developing physical prototype from CAD model, rapid prototyping mainly focuses on two key points reducing time and material consumption. So, we have to change from a traditional solid model to building a hollowed prototype. In this paper, a new method is presented to hollow out solid objects with uniform wall thickness to increase RP efficiency. To achieve uniform wall thickness, it is necessary to generate internal contour by slicing the offset model of an STL model. Due to many difficulties in this method, this paper proposes a new algorithm that computes internal contours computing offset model which is generated from external contour using wall thickness. Proposed method can easily compute the internal contour by slicing the offset surface defined by the sum of circle swept volumes of external contours without actual offset and the circle wept volumes. Internal contour existences are confirmed by using the external point. Presented algorithm uses the 2D geometric algorithm allowing RP implementation more efficient. Various examples have been tested with implementation of the algorithm, and some examples are presented for illustration.

주파수합성기의 Phase Noise 예측 및 3차 PLL 시스템에서의 1/f Noise Modeling (The Phase Noise prediction and the third PLL systems on 1/f Noise Modeling of Frequency Synthesizer)

  • 조형래;성태경;김형도
    • 한국정보통신학회논문지
    • /
    • 제5권4호
    • /
    • pp.653-660
    • /
    • 2001
  • 본 논문에서는 주파수합성기에서 가장 큰 잡음원인 VCO 및 각 단에서 발생하는 위상잡음 의 offset주파수에 따른 변화를 예측하기 위해 2303.15MHz의 주파수합성기를 설계하고 Lascari의 예측방법 을 이용하여 모델링 하였다. 또한, VCO에서 발생되는 여러 중첩 형태로 된 위상잡음중 저주파대역에서 문제가 되는 1/f noise를 3차 시스템에서 분석하였다. 3차 시스템에서는 해석이 복잡하므로 수학적인 분석을 통하여 1/f noise를 예측한다는 것이 어렵지만 pseudo-damping factor의 도입으로 3차 시스템에서의 1/f noise variance의 해석이 용이 하도록 시도하였고 이를 2차 시스템과 비교.분석하였다. 그 결과, tcxo의 경우 위상잡음이 루프 통과 전 10 kHz offset 주파수에서 -160dBc/Hz, 루프 통과 후 -162.6705dBc/Hz, 100 kHz offset 주파수에서 -180dBc/Hz, 루프 통과 후 -560dBc/Hz로 VCO의 위상잡음에 비해 offset주파수에 따라 루프 통과 후 급격히 감쇠 됨을 알 수 있었다. 2차와 3차 시스템에서의 잡음대역폭과 그 variance factor를 연관하여 3차 시스템에서 의 variance가 2차 시스템의 variance보다 크게 발생함을 알 수 있었다.

  • PDF

옵셋팅을 위한 정규 삼각망 추출 (Extracting a Regular Triangular Net for Offsetting)

  • 정원형;정춘석;신하용;최병규
    • 한국CDE학회논문집
    • /
    • 제9권3호
    • /
    • pp.203-211
    • /
    • 2004
  • In this paper, we present a method of extracting a regular 2-manifold triangular net from a triangular net including degenerate and self-intersected triangles. This method can be applied to obtaining an offset model without degenerate and self-intersected triangles. Then this offset model can be used to generate CL curves and extract machining features for CAPP The robust and efficient algorithm to detect valid triangles by growing regions from an initial valid triangle is presented. The main advantage of the algorithm is that detection of valid triangles is performed only in valid regions and their adjacent selfintersections, and omitted in the rest regions (invalid regions). This advantage increases robustness of the algorithm. As well as a k-d tree bucketing method is used to detect self-intersections efficiently.

Touch Screen Sensing Circuit with Rotating Auto-Zeroing Offset Cancellation

  • Won, Dong-Min;Kim, HyungWon
    • Journal of information and communication convergence engineering
    • /
    • 제13권3호
    • /
    • pp.189-196
    • /
    • 2015
  • In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

A Transimpedance Amplifier Employing a New DC Offset Cancellation Method for WCDMA/LTE Applications

  • Lee, Cheongmin;Kwon, Kuduck
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제16권6호
    • /
    • pp.825-831
    • /
    • 2016
  • In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-to-noise ratio degradation. It also reduces area and power consumption. It was designed in a $0.13{\mu}m$ deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of $80dB{\Omega}$, an input-referred noise current lower than 0.9 pA/${\surd}$Hz, an out-of-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is $0.46mm{\times}0.48mm$.