• Journal of Welding and Joining
• /
• v.18 no.3
• /
• pp.89-96
• /
• 2000

As solder becomes small and fine, the reliability and solderability of solder joint are the critical issue in present electronic packaging industry. Besides the use of lead(Pb) containing solders for the interconnections of microelectronic subsystem assembly and packaging has enviromental problem. In this study, using Sn/Pb and Sn/Ag eutectic solder paste, in order to obtain decrease of solder joint strength with increasing aging time, initial solder joint strength and aging strength after 1000 hour aging at $100^{\circ}C$ were measured by peel test. And in order to obtain the growth of intermetallic compound(IMC) layer thickness, IMC layer thickness was measured by scanning electron microscope(SEM). As a result, solder joint strength was decreased with increasing aging time. The mean IMC layer thickness was increased linearly with the square root of aging time. The diffusion coefficient(D) of IMC layer was found to $1.29{\times}10^{-13}{\;}cm^2/s$ at using Sn/Pb solder paste, 7.56{\times}10^{-14}{\textrm}{cm}^2/s$ at using Sn/Ag solder paste.

• Transactions on Electrical and Electronic Materials
• /
• v.10 no.3
• /
• pp.71-74
• /
• 2009

Electroplated Cu is a cost efficient metallization method in microelectronic packaging applications. Typically in 3-D chip staking technology, utilizing through silicon via (TSV), electroplated Cu metallization is inevitable for the throughput as well as reducing the cost of ownership (COO).To achieve a comparable film quality to sputtering or CVD, a pre-cleaning process as well as plating process is crucial. In this research, atmospheric plasma is employed to reduce the usage of chemicals, such as trichloroethylene (TCE) and sodium hydroxide (NaHO), by substituting the chemical assisted organic cleaning process with plasma surface treatment for Cu electroplating. By employing atmospheric plasma treatment, marginally acceptable electroplating and cleaning results are achieved without the use of hazardous chemicals. The experimental results show that the substitution of the chemical process with plasma treatment is plausible from an environmentally friendly aspect. In addition, plasma treatment on immersion Sn/Cu was also performed to find out the solderability of plasma treated Sn/Cu for practical industrial applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.11a
• /
• pp.308-312
• /
• 2003

The packaging of the integrated circuits requires knowledge of ceramics and metals to accommodate the fabrication of modules that are used to construct subsystems and entire systems from extremely small components. Composite ceramics ($Al_2O_3-SiO_2$) were tested for substrates. A stress analysis was conducted for a linear work-hardening metal cylinder embedded in an infinite ceramic matrix. The bond between the metal and ceramic was established at high temperature and stresses developed during cooling to room temperature. The calculations showed that the stresses depend on the mismatch in thermal expansion, the elastic properties, and the yield strength and work hardening rate of the metal. Experimental measurements of the surface stresses have also been made on a $Cu/Al_2O_3-SiO_2$ ceramic system, using an indentation technique. A comparison revealed that the calculated stresses were appreciably larger than the measured surface stresses, indicating an important difference between the bulk and surface residual stresses. However, it was also shown that porosity in the metal could plastically expand and permit substantial dilatational relaxation of the residual stresses. Conversely it was noted that pore clusters were capable of initiating ductile rupture, by means of a plastic instability, in the presence of appreciable tri-axiality. The role of ceramics for packaging of microelectronics will continue to be extremely challenging.

• Korean Journal of Materials Research
• /
• v.34 no.3
• /
• pp.163-169
• /
• 2024

As the limitations of Moore's Law become evident, there has been growing interest in advanced packaging technologies. Among various 3D packaging techniques, Cu-SiO₂ hybrid bonding has gained attention in heterogeneous devices. However, certain issues, such as its high-temperature processing conditions and copper oxidation, can affect electrical properties and mechanical reliability. Therefore, we studied depositing only a heterometal on top of the Cu in Cu-SiO₂ composite substrates to prevent copper surface oxidation and to lower bonding process temperature. The heterometal needs to be deposited as an ultra-thin layer of less than 10 nm, for copper diffusion. We established the process conditions for depositing a Co film using a Co(EtCp)₂ precursor and utilizing plasma-enhanced atomic layer deposition (PEALD), which allows for precise atomic level thickness control. In addition, we attempted to use a growth inhibitor by growing a self-assembled monolayer (SAM) material, octadecyltrichlorosilane (ODTS), on a SiO₂ substrate to selectively suppress the growth of Co film. We compared the growth behavior of the Co film under various PEALD process conditions and examined their selectivity based on the ODTS growth time.

• Journal of the Korean institute of surface engineering
• /
• v.56 no.3
• /
• pp.180-184
• /
• 2023

Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm². Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.

• Journal of the Korean Society for Precision Engineering
• /
• v.31 no.10
• /
• pp.857-863
• /
• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• Design & Manufacturing
• /
• v.2 no.3
• /
• pp.28-31
• /
• 2008

In recent, the demand of high-productivity injection mold is increased because of the growth of international packaging market which is induced by an increase of population. The increase of productivity leads to the large-capacity injection molding machine and peripheral devices. For solving this problem, the stack mold which is based on the exsiting machine and device has researched in advanced countries actively. In this paper, as the preliminary research of stack mold development, the stack mold which has 2 level ${\times}4$ cavity was designed and fabricated. Besides, the motion and structural analysis were performed to verify the stability of developed stack mold.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.5
• /
• pp.621-627
• /
• 2011

In this paper, we analysed performance for on-wafer GaN HEMT using load-pull in X-band, and studied optimum impedance point based on analysis result. We suggested method of optimum performance device by analysis of optimum impedance for solid state device on-wafer condition before packaging. The measured device is gate length 0.25um, and gate width is 400um, 800um. device 400um is performed $P_{sat}$=33.16dBm, PAE=67.36%, Gain=15.16dBm, and device 800um is performed $P_{sat}$=35.91dBm, PAE=69.23%, Gain=14.87dBm.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.4
• /
• pp.31-36
• /
• 2015

The demand for multi-functionality, high density, high performance, and miniaturization of IC devices has caused the technology paradigm shift for electronic packaging. So, thermal management of new packaged chips becomes a bottleneck for the performance of next generation devices. Among various thermal solutions such as heat sink, heat spreader, TIM, thermoelectric cooler, etc. on-chip liquid cooling module was investigated in this study. Micro-channel was fabricated on Si wafer using a deep reactive ion etching, and 3 different micro-channel designs (straight MC, serpentine MC, zigzag MC) were formed to evalute the effectiveness of liquid cooling. At the heating temperature of $200^{\circ}C$ and coolant flow rate of 150ml/min, straight MC showed the high temperature differential of ${\sim}44^{\circ}C$ after liquid cooling. The shape of liquid flowing through micro-channel was observed by fluorescence microscope, and the temperarue differential of liquid cooling module was measuremd by IR microscope.

• Journal of the Microelectronics and Packaging Society
• /
• v.30 no.3
• /
• pp.1-10
• /
• 2023

Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.