• 제목/요약/키워드: 3D Packaging

검색결과 422건 처리시간 0.024초

3D IC 열관리를 위한 TSV Liquid Cooling System (TSV Liquid Cooling System for 3D Integrated Circuits)

  • 박만석;김성동;김사라은경
    • 마이크로전자및패키징학회지
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    • 제20권3호
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    • pp.1-6
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    • 2013
  • TSV는 그동안 3D IC 적층을 하는데 핵심 기술로 많이 연구되어 왔고, RC delay를 줄여 소자의 성능을 향상시키고, 전체 시스템 사이즈를 줄일 수 있는 기술로 각광을 받아왔다. 최근에는 TSV를 전기적 연결이 아닌 소자의 열관리를 위한 구조로 연구되고 있다. TSV를 이용한 liquid cooling 시스템 개발은 TSV 제조, TSV 디자인 (aspect ratio, size, distribution), 배선 밀도, microchannel 제조, sealing, 그리고 micropump 제조까지 풀어야 할 과제가 아직 많이 남아있다. 그러나 TSV를 이용한 liquid cooling 시스템은 열관리뿐 아니라 신호 대기시간(latency), 대역폭(bandwidth), 전력 소비(power consumption), 등에 크게 영향을 미치기 때문에 3D IC 적층 기술의 장점을 최대로 이용한 차세대 cooling 시스템으로 지속적인 개발이 필요하다.

Basic Research on 3D Cultural Heritage Packaging Technology Using Thermoplastic Polyurethane Elastomers

  • Oh, Seung-Jun;Wi, Koang-Chul
    • 보존과학회지
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    • 제37권1호
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    • pp.55-62
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    • 2021
  • This study investigated mechanical property changes by measuring compression factors, resilience, and compressive strength according to packaging pattern and filling rate to identify the applicability of cultural heritage packaging using thermoplastic polyurethane elastomers (TPU). Research results indicate that the cross-shaped 3D pattern showed the best resilience when the internal filling rate was 20%, while the octet pattern was the best when the filling rate was either 40 and 60%. The octet pattern had the best mechanical properties and stability with resistance capacities of 20.79 kgf/cm2, 40.40 kgf/cm2, and 82.23 kgf/cm2 at 38%, 39%, and 40% recovery speeds, respectively, depending on the internal filling rate (20, 40, 60%). Based on these results, basic data on the applicability, stability, and reliability of 3D cultural heritage packaging materials using TPU materials were obtained.

3차원 패키징용 TSV의 열응력에 대한 열적 전기적 특성 (A study on Electrical Characteristic and Thermal Shock Property of TSV for 3-Dimensional Packaging)

  • 정일호;기세호;정재필
    • 마이크로전자및패키징학회지
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    • 제21권2호
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    • pp.23-29
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    • 2014
  • Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

3D Packaging : Where All Technologies Come Together

  • 김영철
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2006년도 SMT/PCB 기술세미나
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    • pp.139-151
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    • 2006
  • [ $\bullet$ ] 3D is proliferating in all package types $\bullet$ Thin packages challenge all assembly technologies $\bullet$ Package assembly and test are closely coupled and design for testability is imperative to success

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IoT 적용을 위한 다종 소자 전자패키징 기술 (Heterogeneous Device Packaging Technology for the Internet of Things Applications)

  • 김사라은경
    • 마이크로전자및패키징학회지
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    • 제23권3호
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    • pp.1-6
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    • 2016
  • IoT 적용을 위해서는 다종 소자를 높은 connectivity 밀도로 집적화시키는 전자패키징 기술이 매우 중요하다. FOWLP 기술은 입출력 밀도가 높고, 소자의 집적화가 우수하고, 디자인 유연성이 우수하여, 최근 개발이 집중되고 있는 기술이다. 웨이퍼나 패널 기반의 FOWLP 기술은 초미세 피치 RDL 공정 기술과 몰딩 기술 개발이 최적화 되어야 할 것이다. 3D stacking 기술 특히 웨이퍼 본딩 후 TSV를 제조하는 방법(via after bonding)은 가격을 낮추면서 connectivity를 높이는데 매우 효과적이라 하겠다. 하지만 저온 웨이퍼 본딩이나 TSV etch stop 공정과 같이 아직 해결해야할 단위 공정들이 있다. Substrate 기술은 두께를 줄이고 가격을 낮추는 공정 개발이 계속 주목되겠지만, 칩과 PCB와의 통합설계(co-design)가 더욱 중요하게 될 것이다.

국내 반도체 첨단패키징 R&D 정책방향: 산학연 전문가 조사를 중심으로 (Exploring R&D Policy Directions for Semiconductor Advanced Packaging in Korea Based on Expert Interviews)

  • 민수진;박종현;최새솔
    • 전자통신동향분석
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    • 제39권3호
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    • pp.1-12
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    • 2024
  • As the demand for high-performance semiconductors, such as chips for artificial intelligence and high-bandwidth memory devices, increases along with the limitations of ultrafine processing technology in the semiconductor in-line process, advanced packaging becomes an increasingly important breakthrough technology for further improving semiconductor performance. Major countries, including Korea, the United States, Taiwan, and China, and large companies are strengthening their technological industry capabilities through the development of advanced packaging technology and policy support. Nevertheless, Korea has a lower level of development of related technologies by approximately 66% compared with the most advanced countries. Therefore, we aim to discover the needs for an advanced packaging research and development (R&D) policy through written expert interviews and importance satisfaction analysis. As a result, various implications for R&D policy directions are suggested to strengthen the technological capabilities and R&D ecosystem of the Korean advanced packaging technology.