• The monthly packaging world
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• s.262
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• pp.45-53
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• 2015

• The monthly packaging world
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• s.101
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• pp.168-171
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• 2001

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.1-6
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• 2013

3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D IC technology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging. However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturing yield, and device test. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling system has been reviewed as one of device cooling methods for the next generation thermal management.

• Journal of Conservation Science
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• v.37 no.1
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• pp.55-62
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• 2021

This study investigated mechanical property changes by measuring compression factors, resilience, and compressive strength according to packaging pattern and filling rate to identify the applicability of cultural heritage packaging using thermoplastic polyurethane elastomers (TPU). Research results indicate that the cross-shaped 3D pattern showed the best resilience when the internal filling rate was 20%, while the octet pattern was the best when the filling rate was either 40 and 60%. The octet pattern had the best mechanical properties and stability with resistance capacities of 20.79 kgf/cm², 40.40 kgf/cm², and 82.23 kgf/cm² at 38%, 39%, and 40% recovery speeds, respectively, depending on the internal filling rate (20, 40, 60%). Based on these results, basic data on the applicability, stability, and reliability of 3D cultural heritage packaging materials using TPU materials were obtained.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.23-29
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• 2014

Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

• The monthly packaging world
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• s.187
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• pp.87-91
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• 2008

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.02a
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• pp.139-151
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• 2006

[ $\bullet$ ] 3D is proliferating in all package types $\bullet$ Thin packages challenge all assembly technologies $\bullet$ Package assembly and test are closely coupled and design for testability is imperative to success

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.699-700
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• 2009

• Electronics and Telecommunications Trends
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• v.39 no.3
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• pp.1-12
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• 2024

As the demand for high-performance semiconductors, such as chips for artificial intelligence and high-bandwidth memory devices, increases along with the limitations of ultrafine processing technology in the semiconductor in-line process, advanced packaging becomes an increasingly important breakthrough technology for further improving semiconductor performance. Major countries, including Korea, the United States, Taiwan, and China, and large companies are strengthening their technological industry capabilities through the development of advanced packaging technology and policy support. Nevertheless, Korea has a lower level of development of related technologies by approximately 66% compared with the most advanced countries. Therefore, we aim to discover the needs for an advanced packaging research and development (R&D) policy through written expert interviews and importance satisfaction analysis. As a result, various implications for R&D policy directions are suggested to strengthen the technological capabilities and R&D ecosystem of the Korean advanced packaging technology.