• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.5
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• pp.51-56
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• 1995

The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

• Journal of Power Electronics
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• v.2 no.3
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• pp.212-219
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• 2002

A novel mode of parallel operation of a modular 3-phase AC-DC flyback converter for power factor correction along with tight regulation was recently analyzed and presented. The advantage of the proposed converter does not require expensive high voltage and high current devices that are normally needed in popular boost type 3-phase converter. In this paper tile detailed small signal analysis of the modular 3-phase AC-DC flyback converter is provided for control purpose and also experimental results are included to confirm the validity of the analysis.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.987-993
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• 2003

The module UPS can flexibly implement expansion of power system capacities. Furthermore, it can be used to build up the parallel redundant system to improve the reliability of power system operation. To realize the module UPS, load sharing without interconnection among parallel connecting modules as well as a small scale and lightweight topology is necessary. In this paper, the three-arm converter/inverter is compared with the general full-bridge and half-bridge topology from a practical point of view and chosen as the module UPS topology. The switching control approaches based on a pulse width modulation of the converter and inverter of the system are presented independently The frequency and voltage droop method is applied to parallel operation control to achieve load sharing. Two prototype 3kVA modules are designed and implemented to confirm the effectiveness of the proposed approaches. Experimental results show that the three-arm UPS system has a high power factor, a low distortion of output voltage and input current, and good load sharing characteristic.

• 한국태양에너지학회:학술대회논문집
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• 2008.04a
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• pp.43-48
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• 2008

Through simulations and field experiment on A.C. parallel operation of both Utility Interactive Photovoltaic System and Diesel Engine Revolving Field Type Synchronous Generator, following factors have been found. First, the inverter should be operated in three modes of frequency(mode.1: ${\pm}$0.3Hz, mode.2: ${\pm}$1Hz, mode.3: ${\pm}$2Hz) as default, considering properties of operating Synchronous Generator. Second, as a result of supplying 13.5kW of residual power, it has been found that Synchronous Generator takes the power input only as reactive power, because it was electrically stable with frequency of 60.14Hz and high voltage of 222.3V even when power factor was -0.94. Besides, it was mechanically stable, too, because the quake, noise, and temperature of Synchronous Generator in this case were 7.5mm/s, 97dB, and $6^{\circ}C$ respectively, which were lower than normal load connection of 145.6kW; 11.03mm/s. Thus, load share of Revolving Field Type Synchronous Generator reduces according to the supply of Photovoltaic System to the load power. In this experiment, 200kW of Synchronous Generator and 40kW of Photovoltaic System were operated in parallel. The load share was 20% in maximum. and 11.1lit/hr of fuel was saved.

• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.39-47
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• 2023

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.991-996
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• 2010

In this paper, we designed a parallel I/O control system using IEEE 1284 operating modes and implemented remote control communication under the internet environment. The IEEE 1284 standard defines an interface compatible with several distinct operation modes and brings higher performance to the PC parallel port. Therefore, parallel port devices become easier to configure and simplify interface because new operating systems bring PnP function to the parallel port with the Device/ID identification sequence. With these enhancements, the parallel port become an even better low-cost, readily available I/O port on the PC.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.244-251
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• 2010

High speed motors have been widely used in industries to reduce system size and improve power conversion efficiency. However, the high speed motors sometimes suffer from core losses caused by PWM current ripple; noting that the phase inductance, $L_s$, of high speed motor is smaller than that of ordinary motors. In the proposed topology, three PWM inverters are connected in parallel through nine coupled inductors. Compared to the PWM current ripple of the conventional single inverter system, that of the proposed scheme can be conspicuously reduced without the voltage drop at the inductors. In this paper a theoretical analysis of the output voltage of the proposed topology is presented, and then the validity of the proposed method is verified by experimental results.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.89-99
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• 1995

One of the hardest problems that limit real application of production system is its slowness. One way to overcome this problem is to speed up the matching operation which occupies more than 90% of the total execution time. In this paper, we try to speed up the matching operation with parallel execution of a typical pattern matching algorithm, RETE, in a multiprocessor environment, This requires not only to make partitions of the rules but also to allocate the partitioned rules to processors, respectively. A partition strategy is proposed to make groups of similar rules by evaluating the similarity of rules according to the number of common conditions between rules. An allocation strategy is proposed to make the load of each processor even by assigning the different priority to the group of rules according to the expected amount of time required for matching operation. To compare with the existing methods, we perform simulation using OPS5 sample programs. The simulation results show that the proposed methods can improve the performance of production system.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.156-158
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• 1998

This paper presents parallel operation of two 3-phase PWM converters whose Power and control schemes can be directly applied to a large capacity system. This paper describes power circuit, dc voltage regulation, input power factor correction and balancing load control of two converters. Switching device Is IGBT and CPU of control is 32-bit floating point DSP for real time instantaneous control. Simulations and experimental results for 20kw model conform the validity of proposed schemes.