• Biotechnology and Bioprocess Engineering:BBE
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• v.10 no.4
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• pp.304-308
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• 2005

The response of IPTG induction was investigated through the monitoring of the alkali consumption rate and buffer capacity during the cultivation of recombinant E. coli BL21 (DE3) harboring the plasmid pRSET-LacZ under the control of lac promoter. The rate of alkali consumption increased along with cell growth, but declined suddenly after approximately 0.2 h of IPTG induction. The buffer capacity also declined after 0.9 h of IPTG induction. The profile of buffer capacity seems to correlate with the level of acetate production. The IPTG response was monitored only when introduced into the mid-exponential phase of bacterial cell growth. The minimum concentration of IPTG for induction, which was found out to be 0.1 mM, can also be monitored on-line and in-situ. Therefore, the on-line monitoring of alkali consumption rate and buffer capacity can be an indicator of the metabolic shift initiated by IPTG supplement, as well as for the physiological state of cell growth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.42-45
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• 2002

A low power SDRAM output buffer with reduced power line noise and feedthrough current is presented. In multi I/O SDRAM output buffer, feedthrough current as well as the corresponding power dissipation are reduced utilizing proposed undershoot protection circuits. Ground bounce is minimized by the pull down driver using intelligent feedback scheme. Ground bounce noise is reduced by 66.3% and instantaneous and average power are reduced by 27.5% and 11.4%, respectively.

• Journal of IKEEE
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• v.19 no.1
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• pp.10-17
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• 2015

In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.57-64
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• 2021

The domestic semiconductor industry can produce various products that will satisfy customer needs by diversifying assembly parts and increasing compatibility between them. It is necessary to improve the production line as a method to reduce the work-in-process inventory (WIP) in the assembly line, the idle time of the worker, and the idle time of the process. The improvement of the production line is to balance the capabilities of each process as a whole, and to determine the timing of product input or the order of the work process so that the time required between each process is balanced. The purpose of this study is to find the optimal WIP and buffer size through SA (Simulated Annealing) that minimizes lead time while matching the number of two parts in a parallel assembly line with bottleneck process. The WIP level and buffer size obtained by the SA algorithm were applied to the CONWIP and DBR systems, which are the existing production systems, and the simulation was performed by applying them to the new hybrid production system. Here, the Hybrid method is a combination of CONWIP and DBR methods, and it is a production system created by setting new rules. As a result of the Simulation, the result values were derived based on three criteria: lead time, production volume, and work-in-process inventory. Finally, the effect of the hybrid production method was verified through comparative analysis of the result values.

• Journal of Industrial Technology
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• v.16
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• pp.207-216
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• 1996

This paper develops an algorithm for throughput of a 3-stage flow line with job inspection stations, limited buffer capacity, and exponential processing times. Each stage consists of a single workstation, and an infinite number of jobs always waits in front of the first workstation. Blocking may occur when a processed job is waiting at one workstation for another workstation to become available. Numerical example results provide insights into the problems related to quality inspection and measure of performance of flow lines.

• Journal of the Korea Society for Simulation
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• v.9 no.1
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• pp.1-9
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• 2000

When a new manufacturing line is constructed, its production capacity can be substantially affected in its design stage. Computer simulation often provides better design by evaluating feasible alternatives. In this paper we study an automobile engine manufacturing line which is under construction. Three alternatives are considered in the design; (1) to use machining tools of longer life; (2) to reassign the buffer space to each sequential processes while maintaining the same total buffer length; and (3) to reduce the machine repair time to 30 minutes using TPM and maintenance team. Simulation results using AutoMod indicates that employing the three alternatives will save about 1.5 million dollars per year.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.28-35
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• 1998

In this paper, an NxN input-buffered crosspoint packet switch which selects a Head of the Line, HOL, packet in contention randomly is analyzed with a new approach. The approach is based on both a Markov chain representation of the input buffer and the probability that a HOL packet is successfully served. The probability as a function of N is derived, and it makes it possible to express the average packet delay and the average number of packets in the buffer as a function of N. The contention resolution policy based on the occupancy of the input buffer is also presented and analyzed with this same approach and the relationship between two selection policies is analyzed in terms of the occupancy of the input buffer.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Journal of Ocean Engineering and Technology
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• v.9 no.2
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• pp.83-88
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• 1995

In this paper, the solid modeller suitable for PC was developed for Top-down 3-D representation and analysis of fixed offshore structures. Also solid modelling and hidden line removal were conducted in order to visualize the offshore structures based on the scan line z-buffer algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.