• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.3
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• pp.17-23
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• 2020

This paper proposes a simulation model using an equivalent circuit for the development of an MMC system. The MMC has been chosen as the most suitable topology for high voltage power transmission, such as a voltage-type HVDC, and it has dozens to hundreds of sub-modules in the form of a half-bridge or full-bridge connected in series. A simulation study is essential for the development of an MMC algorithm. On the other hand, it is virtually impossible to construct and implement MMC simulation models, including hundreds or thousands of switching devices. Therefore, this paper presents an MMC equivalent model, which is easily expandable and implemented by modeling the dynamic characteristics. The voltage and current equation of the equivalent circuit was calculated using the direction of the arm current and switching signal. The model was implemented on Matlab/Simulink. In this paper, to show the validity of the model developed using Matlab/Simulink, the simulation results of a five-level MMC using the real switching element and the proposed equivalent model are shown. The validity of the proposed model was verified by showing that the current and voltage waveform in the two models match each other.

• Korean Institute of Interior Design Journal
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• v.14 no.5 s.52
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• pp.254-261
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• 2005

This paper presents an attempt to develop a visual programming language-based 3D virtual reality authoring tool intended to compose virtual interior space. The rapid development of digital technology and the wide spread of the Intenet have expanded the different uses of virtual reality in a number of applications ranging from interior design to building maintenance. In particular, the construction of cyber spaces based on existing interior spaces is becoming increasingly important. Current research, however, remains at the level of converting 3D models into virtual reality models, despite practitioners' needs for structural space models. Moreover, commercial tools to build virtual reality space have the disadvantage of targeting people who have professional knowledge of computer programs and computer graphics. Accordingly, the 3D virtual reality authoring tool developed in this research - called the VESL system - enables virtual and structural space to be easily composed using intuitive and interactive visual interfaces, which are based on visual programming techniques. The VESL system also provides an XML based semantic description of interior space, to be used to describe interior space information. We anticipate that the virtual reality spaces composed by this system will be of considerable use in the fields of architecture and interior design. Further research issues identified at the end of the research include developing a converter/filter for transforming Internet virtual reality standard language, or VRML, and evaluating the application of the system for practical use.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• Journal of Fashion Business
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• v.4 no.4
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• pp.17-28
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• 2000

The purpose of this study is to analyze the recognition of and the preference for a fashion specialist among students from 4-year and 2-year colleges in Taegu, in order to provide basic data for the effective management methods for the students. The objects of the survey were students in Taegu and Kyungbuk province; 287 students from 4-year colleges and 430 students from 2-year colleges, making the total of 717 students. The survey tool was a questionnaire, which consists of 7 general questions, 7 major curriculum related questions, and 6 questions regarding the information about a fashion specialist, and students career plan. It also contains 3-level Licurt type questionnaire on the recognition of and the preference for a fashion specialist from 20 professional fields. SPSS is used for frequency, percentage, average, standard deviation, $x^2$-test and ANOVA. The results of this study are as follows: 1. The students' motivation in choosing their major as clothing and fashion design was out of independent career plan (86.7%). They were quite content with their major but were unsatisfactory with the current curriculum. 2. The subjects students thought necessary in preparing to be a fashion specialist were pattern, clothing construction (40.1%), clothing design (33.7%), and fashion marketing (18.9%). The answer to the question about the most important subject in the future was fashion marketing (57.2%). 3. What students consider most in choosing a job was aptitude and ability (70.8%). The most preferable clothing types that students want to work with after graduation were womens clothing (52.1%) and wedding dress (18.1%). 4. The means of getting information on a fashion specialist were magazines or broadcasting (72%) and school lectures (20.6%), and there was a significant deference among colleges. 5. Fashion coordinator was the highest recognized specialist (2.64) and the lowest was fashion converter (1.23) among other fashion specialists. 4-year college students had higher recognition in all areas (20 areas) than 2-year college students, and there was a significant deference among colleges in 20 areas.

• Journal of Radiation Protection and Research
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• v.41 no.3
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• pp.185-190
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• 2016

Background: In order to measure neutron energy spectra, the conventional Bonner Sphere Spectrometers (BSS) are widely used. In this spectrometer, several measurements with different size Bonner spheres are required. Operators should, therefore, place these spheres in several times to a measurement point where radiation dose might be relatively high. In order to reduce this effort, novel neutron energy spectrometer using an onion-like single Bonner sphere was proposed in our group. This Bonner sphere has multiple sensitive spherical shell layers in the single sphere. In this spectrometer, a band-shaped thermal neutron detection medium, which consists of a LiF-ZnS mixed powder scintillator sheet and a wavelength-shifting (WLS) fiber readout, was looped to each sphere at equal angular intervals. Amount of LiF neutron converter is reduced near polar region, where the band-shaped detectors are concentrated, in order to uniform the directional sensitivity. The LiF-ZnS mixed powder has an advantage of extremely high light yield. However, since it is opaque, scintillation photons cannot be collect uniformly. This type of detector shows no characteristic shape in the pulse height spectrum. Subsequently, it is difficult to set the pulse height discrimination level. This issue causes sensitivity fluctuation due to gain instability of photodetectors and/or electric modules. Materials and Methods: In order to solve this problem, we propose to replace the LiF-ZnS mixed powder into a flexible and Transparent RUbber SheeT type $LiCaAlF_6$ (TRUST LiCAF) scintillator. TRUST LiCAF scintillator can show a peak shape corresponding to neutron absorption events in the pulse height spectrum. Results and Discussion: We fabricated the prototype detector with five sensitive layers using TRUST LiCAF scintillator and conducted basic experiments to evaluate the directional uniformity of the sensitivity. Conclusion: The fabricated detector shows excellent directional uniformity of the neutron sensitivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1095-1101
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• 2012

This paper presents a design of a BLDC servo motor control system for the auto process of assembly and supply using DSP(Digital Signal Processor) controller and IGBT driver. The assembly and supply auto processing system needs torque, speed, position control of servo motor for variable action. This paper implements those servo control with vector control and space vector PWM(Pulse Width Modulation) technique. As CPU of controller, TMS320F240 DSP was adopted because it has PWM waveform generator, A/D converter, SPI(Serial Peripheral Interface) port and many input/output port etc. This control system consists of 3-level hierarchy structure that main host PC manages three sub DSP system which transfer downward command and are monitoring the states of end servo controllers. Each sub DSP system operates eight BLDC servo controllers which control BLDC motor using DSP and IPM. Between host system and sub DSP communicate with RS-422, between main processor and controller communicate with SPI port.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.3
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• pp.171-178
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• 2014

From now on, in order to meet more stringer diesel emission standard, diesel vehicle should be equipped with emission after-treatment devices as NOx reduction catalyst and particulate filters. Urea-SCR is being developed as the most efficient method of reducing NOx emissions in the after-treatment devices of diesel engines, and recent studies have begun to mount the urea-SCR device for diesel passenger cars and light duty vehicles. That is because their operational characteristics are quite different from heavy duty vehicles, urea solution injection should be changed with other conditions. Therefore, the number and diameter of the nozzle, injection directions, mounting positions in front of the catalytic converter are important design factors. In this study, major design parameters concerning urea solution injection in front of SCR are optimized by using a CFD analysis and Taguchi method. The computational prediction of internal flow and spray characteristics in front of SCR was carried out by using STAR-CCM+7.06 code that used to evaluate $NH_3$ uniformity index($NH_3$ UI). The design parameters are optimized by using the $L_{16}$ orthogonal array and small-the-better characteristics of the Taguchi method. As a result, the optimal values are confirmed to be valid in 95% confidence and 5% significance level through analysis of variance(ANOVA). The compared maximize $NH_3$ UI and activation time($NH_3$ UI 0.82) are numerically confirmed that the optimal model provides better conversion efficiency of $NH_3$. In addition, we propose a method to minimize wall-wetting around the urea injector in order to prevent injector blocks caused by solid urea loading. Consequently, the thickness reduction of fluid film in front of mixer is numerically confirmed through the mounting mixer and correcting injection direction by using the trial and error method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.