• 한국미생물·생명공학회지
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• 제32권2호
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• pp.190-194
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• 2004

The gene product of dctD (DctD) activates transcription from the dctA promoter regulatory region by the $\sigma^{54}$ -holoenzyme form ofRNA polymerase ($E\sigma^{54}$ ) in Rhizobium meliloti and R. leguminosarum. The Escherichia coli integration host factor (IHF) stimulated DctD-mediated activation from the dctA promoter regulatory region of R. leguminosarum but not R. meliloti. In the absence of UAS, IHF inhibited DctD-mediated activation from both of these promoter regulatory regions. IHF also inhibited activation from R. leguminosarum dctA by nitrogen regulatory protein C (NtrC), another activator of $E\sigma^{54}$ but not by one which lacks a specific binding site in this promoter regulatory region. IHF, however, stimulated NtrC-mediated activation from the R. meliloti dctA promoter. Upon removal of the UAS, IHF inhibited NtrC-mediated transcription activation from the R. meliloti dctA promoter regulatory region. These data suggest that IHF likely faciliates productive contacts between the activators NtrC or DctD and $E\sigma^{54}$ to stimulate activation from dctA promoter.

• 방송공학회논문지
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• 제22권3호
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• pp.366-374
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• 2017

TV나 디지털 사이니지와 같은 화면표시장치들이 점점 커져감에 따라, 미디어의 종류가 UHD, 파노라마, 퍼즐형 미디어와 같은 광각의 미디어로 변하고 있다. 특히, 파노라마 및 퍼즐형 미디어는 스티칭을 통해 복수개의 카메라로 촬영된 비디오 클립을 합성한 형태로 구성된다. 그러나, 스티칭 과정의 처리 시간이 오래 걸리기 때문에 실시간 서비스에는 적용하기 어려운 문제가 있다. 따라서 본 논문에서는 스티칠 처리 시간을 감소하기 위한 방법으로, 영상간의 공간적 연관관계를 알려주는 2D Adjacency Matrix를 생성하는 것을 제안한다. Discrete Cosine Transform (DCT)를 사용하여, 비디오 소스의 각 프레임을 공간 영역에서 주파수 영역으로 변환 시킨다. 앞서 언급한 DCT 계수를 기반으로 효과적으로 이미지들의 공간적 연관관계를 알려주는 2D Adjacency Matrix를 생성한다. 본 논문에서는 각각의 비디오 클립들로부터 파노라마 영상과, 퍼즐형 미디어를 생성하기 위해 DCT를 이용한 2D Adjacency matrix 생성 방법을 제안한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.175-178
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• 2003

This paper proposes a stereo image insertion technique on DCT coefficients using the embedded method developed in the digital watermarking in due consideration of compatibility with conventional 2D system such JPEG, and MPEG. In conventional transmission method users with conventional digital TV cannot watch the transmitted 3D image sequence as 2D image, because of affectivity of conventional 3D image compression. To give an answer, in this paper, DCT coefficients are changed according to its disparity on YCbCr channels. Our method can insert stereo images into a conventional image compression method based on DCT.

• 한국정보처리학회논문지
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• 제1권1호
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• pp.81-91
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• 1994

벡터 양자화기를 이용하여 영상의 부호화기를 설계하는데 있어서 2차원 이산여현 변환(2D-Discrete Cosine Transform)에 근거한 DCT 맵(map)과 새로운 부호책(codebook) 설계로서 알고리듬을 제안한다. 영상을 작은 부블럭으로 나누고 2차원 이산여현변환 으로 대부분의 정보를 포함하는 부분, 즉 부호화하기 어려운 부분과 부호화하기 쉬운 적은 정보를 포함하는 영역으로 나누어 맵을 만들고 이 맵에 따라 영상의 중요한 특징 들을 2차원 이산여현변환으로 추출한다. 부호책은 트리 구조에 근거한 2진 트리로 두 영역을 따로 학습세트로 나눔으로서 만들어 진다. 2진 트리의 중간 노드에서 각 학 습 벡터는 그 노드에서의 문턱 값과 비교하여 두개의 아래 노드중 하나에 속하게 된다. 국제 표준화상인 Lenna와 Boat 영상에 대하여 본 알고리듬으로 영상을 부호화했을 때 PNN과 CVQ 알고리듬에 비하여 수행 시간을 줄이고, PNN 알고리듬보다는 각각 약0.45 dB과 0.33 dB만큼, CVQ 알고리듬보다 각각 약 0.05 dB과 0.1 dB만큼 더 좋은 영상의 화질을 얻을 수 있었다.

• 전자공학회논문지B
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• 제33B권2호
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• pp.103-110
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• 1996

In this paper, we propose a unified systolic array for the computation of the 2D discrete cosine transform/discrete sine transform/discrete hartley transform (DCT/DST/DHT). The unified systeolic array for the 2D DCT/DST/DHT is a generalization of the unified systolic array for the 1D DCT/DST/DHT. In order to calculate the 2D transform, we compute 1D transforms along the row, transpose them, and obtain 1D transforms along the column. When we compare the proposed systolic array with the conventional method, our architecture exhibits a lot of advantages in terms of latency, throughput, and the number of PE's. The simulation results using very high speed integrated circuit hardware description language (VHDL), international standard language for hardware description, show the functional validity of the proposed architecture.

• 전자공학회논문지A
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• 제32A권1호
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• pp.234-243
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• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송∙미디어공학회 2016년도 추계학술대회
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• pp.39-42
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• 2016

Since a display device such as TV or signage is getting larger, the types of media is getting changed into wider view one such as UHD, panoramic and jigsaw-like media. Especially, panoramic and jigsaw-like media is realized by stitching video clips, which are captured by different camera or devices. In order to stich those video clips, it is required to find out 2D Adjacency Matrix, which tells spatial relationships among those video clips. Discrete Cosine Transform (DCT), which is used as a compression transform method, can convert the each frame of video source from the spatial domain (2D) into frequency domain. Based on the aforementioned compressed features, 2D adjacency Matrix of images could be found that we can efficiently make the spatial map of the images by using DCT. This paper proposes a new method of generating 2D adjacency matrix by using DCT for producing a panoramic and jigsaw-like media through various individual video clips.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• 정보처리학회논문지:소프트웨어 및 데이터공학
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• 제3권3호
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• pp.135-138
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• 2014

본 논문에서는 2D-DCT와 EHMM 알고리즘을 이용하여 과적합에 강인한 얼굴 표정인식 방법을 고안하였다. 특히, 본 논문에서는 2D-DCT 특징추출을 위한 윈도우 크기를 크게 설정하여 EHMM의 관측벡터를 추출함으로써, 표정인식 성능 향상을 도모하였다. 제안 방법의 성능평가는 공인 CK 데이터베이스와 JAFFE 데이터베이스를 이용하여 수행되었고, 실험 결과로부터 특징추출 윈도우의 크기가 커질수록 표정 인식률이 향상됨을 확인하였다. 또한, CK 데이터베이스를 이용하여 표정 모델을 생성하고 JAFFE 데이터베이스 전체 샘플을 테스트한 결과, 제안 방법은 87.79%의 높은 인식률을 보였으며, 기존의 히스토그램 특징 기반의 표정인식 접근법보다 46.01~50.05%의 향상된 인식률을 보였다.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권2호
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• pp.86-93
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• 2004

The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation Sharing Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.